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Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Transforming Chip Design with Cadence Cerebrus AI Studio

Cadence is transforming chip design with the launch of Cadence Cerebrus ® AI Studio…

Sean Kobayashi
• 1 min read
digital design , featured , agentic ai , designed with cadence , Cadence Cerebrus

Conformal AI Studio: Accelerated LEC/ECO/LP with AI/ML-Driven Enhancements

If you're a chip designer or verification engineer, you have likely spent countless…

David Stratman
• 5 min read
conformal , featured , Digital Implementation , Conformal AI Studio , AI/ML
Digital Design

Latest blogs

2017 Annual HLS Survey Results

As many of you know, Cadence (more correctly, “I”) recently performed an industry…

• 4 min read
High-Level Synthesis , survey , Stratus , HLS

Designing for Low Power… Begin at the Beginning

So you have your RTL written, and it’s time to optimize to reduce power. If that…

• 3 min read
Low Power , high level synthesis , power , HLS

Let Your DRC Fly! Cadence Announces Breakthrough in SoC Physical Verification

This morning we announced our next-generation Pegasus Verification System, the biggest…

• 2 min read
Physical verification , CDNLive , pegasus , DRC , design rule check , silicon signoff

“Great” Hardware Design in a Wireless World

As part three of the “ Making Hardware Design Great Again” series , let’s see how…

• 4 min read
High-Level Synthesis , digital implementation , Digital Implementation , HLS

Have DRC Tools Run Out of Steam? – Part 2

We are continuing the physical verification blog posts with more questions we hear…

• 3 min read
massively scalable , DRC , multithread , distributed processing

Have DRC Tools Run Out of Steam? – Part 1

In the EDA history of design rule check (DRC), there have been two distinct eras…

• 3 min read
Physical verification , DRC , design rule check

Making Hardware Design Great Again in 2017 - Part Deux

In part one of this series, we talked about the role of the hardware designer , specifically…

• 5 min read
High-Level Synthesis , digital implementation , Digital Implementation , HLS

Making Hardware Design Great Again in 2017

Ok, I admit it… that title is a blatant attempt to grab your attention. But it should…

• 4 min read
High-Level Synthesis , digital implementation , Digital Implementation , HLS

Performance, Power, Area. It's All You Need to Know—or Is It?

Whether it's in a technical paper, a pundit's article, or a live discussion with…

• 2 min read
High-Level Synthesis , PPA , Stratus , SystemC , HLS

Five-Minute Tutorial: Innovus Clock Tree Synthesis and Debugger

Hi Everyone, Last time, our Five-Minute Tutorial focused on the new Innovus Placement…

• less than a min read
training , ccopt , clock tree synthesis , debugger , Digital Implementation , Innovus

Hot Summer for the High-Level Synthesis Community

Summer is usually a slow time of the year due to vacations, beautiful weather, and…

• 4 min read
High-Level Synthesis , DAC 2015 , SystemC , Brian Bailey , HLS , SystemC Japan 2015

Five-Minute Tutorial: Innovus Placement Optimization

Hi Everyone, Last time we got a quick look at The Innovus Standard Flow . Now…

• less than a min read
GigaPlace , Timing Optimization , Innovus , Placement

Five-Minute Tutorial: The Innovus Standard Flow

Hi Everyone, Last week I highlighted a video featuring Innovus User Interface…

• less than a min read
design flow , Digital Implementation , Innovus , five minute tutorial

Five-Minute Tutorial: Innovus User Interface Tips

Hi Everyone, No doubt by now you have heard about the Innovus Implementation System…

• less than a min read
UI , Digital Implementation , Innovus , five minute tutorial

Five Things You Didn’t Know About High-level Synthesis

Most of you have heard about the promises of high-level synthesis (HLS). Things like…

• 4 min read
High-Level Synthesis , ECO , Conformal ECO Designer , cadence , Blu Wireless , Forte , Stratus , HLS

High-Level Synthesis: Why Now?

March 27, 2015 – With a title like “Why Now?”, you might expect this to be a sales…

• 2 min read
High-Level Synthesis , EDA , Forte , Stratus , HLS

Five-Minute Tutorial: Inserting Column Power Switches in EDI

Hello my fellow Digital Designers, I'm sorry I haven't been around the blogs much…

• 1 min read
EDI , Low Power , electronic system design , Cadence Online Support , Encounter Digital Implementation , five minute tutorial , power switch

Five-Minute Tutorial: One More Look at EM Models

Just when you thought you were done setting up EM model files, along came another…

• 2 min read
Voltus , Digital Implementation , Power Analysis , EM , five minute tutorial

New Training Class: Get Up to Speed Fast When Migrating to Encounter Digital Implementation…

One question we often hear from experienced physical design engineers migrating to…

• 2 min read
P&R , encounter digital implementation system , place and route , Rapid Adoption Kits , RAKs , physical implementation

Sharing is Learning - New RAKs and Videos for Digital Users on Cadence Support

Friends, you would probably agree that sharing knowledge is a practical way to solve…

• 2 min read
EDI , Encounterer Digital Implementation System , Digital Implementation forums , Tempus , EDI system , Cadence Online Support , digital implementation , Digital Implementation , Encounter Digital Implementation , signoff , timing signoff

Five-Minute Tutorial: Start the New Year with Voltus

Happy New Year to all of our Digital Implementation Blog readers - and also to anyone…

• 2 min read
voltagestorm , vstorm , rail analysis , EPS , vector-based , Voltus , IRdrop , power grid view , Power Analysis , EM , vectorless , five minute tutorial , power , RAKs , power grid library

11 Things I Learned by Browsing Cadence Online Support

I guess by now most of us are already familiar with Rapid Adoption Kits (RAKs). These…

• 3 min read
Digital Implementation forums , How To , Cadence EDI System , power routing , Floorplanning , encounter digital implementation system , beginner , NanoRoute , training , Appnotes , Top Ten , digital implementation , Cadence Encounter Power System , GigaOpt , Digital Implementation , Encounter Digital Implementation , crosstalk , app notes , high performance , Rapid Adoption Kits , encounter power system , OpenAccess , Floorplanning and Prototyping , RAKs , FlipChip

Five-Minute Tutorial: EM Model Files Revisited

Back in January, I posted a Five-Minute Tutorial about creating EM Model files .…

• 2 min read
EDI , qrcTechFile , EM Model , ICT , Techgen , iRCX , EPS , digital implementation , EM Model File , Power Analysis , EM , five minute tutorial

Answers to Top 10 Questions on Performing ECOs in EDI System

Applying ECOs to a design can be complex, stressful and error prone so it's important…

• 6 min read
ECO , Cadence EDI System , LEC , encounter digital implementation system , tips and tricks , Synthesis , mmmc

Five-Minute Tutorial: Set Flip-Chip Bumps as Voltage Sources in EPS/EDI Rail Ana…

When running power and rail analysis for a flip chip, we used to have to spend some…

• 3 min read
EDI , rail analysis , EPS , Five-Minute tutorial , Power Analysis , flip chip , bump

CDNLive High-Performance Track: Do You Have What it Takes to Get Your High-Performance…

Implementing SoCs with embedded processors at advanced nodes has become increasingly…

• 5 min read
ARMv8 , EDI , Low Power , Cortex-A15 , CDNLive , Cortex-A57 , Cortex-A7 , RC-Physical , NVIDIA , Avago , SoC , ccopt , digital , GigaOpt , Digital Implementation , Encounter Digital Implementation , AppliedMicro , high performance , CDNLive Silicon Valley , ARM , CDNLive! Cadence

Five-Minute Tutorial: Create Encounter Power System (EPS) Power-Grid Views For Standard…

In today's tutorial, I'm giving you a sample EPS (Encounter Power System) script…

• 4 min read
power-grid views , Low Power , rail analysis , current density , LEF , EPS , standard cells , Digital Implementation , qrc , Power Analysis , signoff , EM , IR drop , five minute tutorial , encounter power system , power

Quick Reference - 8 Ways to Optimize Power Using Encounter Digital Implementation…

Everyone knows that the increasing speed and complexity of today's designs implies…

• 4 min read
EDI , EDI system , Vt partition , low power tips , leakage , Jaiswal , EDI 11.1 , 8 ways , encounter digital implementation system , Encounter Digital Implementation , optLeakagePower , Leakage Optimization , power optimization , EDI 11 , dynamic power
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