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Would you like to know how to design a complete chip using the RTL-to-GDSII flow? Please join me, Cadence Training and application engineer Sai Srinivas Pamula, for this free technical Training Webinar, RTL-to-GDSII Flow for ASIC Design Using Cadence Tools.
In this free technical Training Webinar, we'll teach you the essential steps in the RTL-to-GDSII design flow using a wide variety of industry-leading Cadence tools—such as the Xcelium Logic Simulator, Modus DFT Software Solution, Genus Synthesis Solution, Conformal technologies, Innovus Implementation System, and Tempus Timing Solution—that provide great power, performance, and area (PPA). You will explore topics like:
Wednesday, December 13 07:00 PST San Jose / 10:00 EST New York / 15:00 GMT London / 16:00 CET Berlin / 17:00 IST Jerusalem / 20:30 IST Bangalore / 23:00 CST Beijing
REGISTER To register for the RTL-to-GDSII Flow for ASIC Design Using Cadence Tools webinar, sign in with your Cadence Support account (email ID and password) to log in to the Learning and Support System. Then select Enroll to register for the session. Once registered, you’ll receive a confirmation email containing all login details. If you don’t have a Cadence Support account, go to Registration Help or Cadence User Registration, and complete the requested information. For questions and inquiries or issues with registration, reach out to email@example.com.
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Learn more about and enroll in the related training course Cadence RTL-to-GDSII Flow Training. The course includes slides with audio, and downloadable laboratory exercises designed to emphasize the topics covered in the lecture. There is also a Digital Badge available for the training.