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Are you interested in reducing the power dissipation of your design? Who wouldn’t? What about taking the advantage of Clock Gating?
Clock Gating is a technique that enables inactive clocked elements to have gating logic automatically inserted. Even though data is loaded into registers very infrequently in most designs, the clock signal continues to toggle at every clock cycle. Often, the clock signal also drives a large capacitive load, making clock signals a major source of dynamic power dissipation. Gating a group of flip-flops that are enabled by the same control signal reduces unnecessary clock toggles. This helps reduce the power dissipation since power is not dissipated during the idle period when the register is shut off by the gating function. Power is saved in the gated-clock circuitry and the logic on the enable circuitry in the original design is removed.
If you indeed seek the best techniques to reduce the power consumption of your design, but all that extra information in the report files seems daunting and hard to interpret, relax! Cadence has you covered with the Training Byte, “Understanding Clock Gating Report and Cells”. This training byte will guide you through the commands and attributes you need to extract the right information from the Clock Gating Report such as:
Further, it will show you how to do analysis in GUI mode of Genus Synthesis Solution to trace back the fanin cone of the flops clock pin to find about the clock gating instances.
Understanding Clock Gating Report and Cells
Enhance the Genus Synthesis Solution experience with more videos: Genus Synthesis Solution: Video Library.
Note: For lab instructions and a downloadable design, enroll in the corresponding trainings like Genus Synthesis Solution v19.1 (Online) or join our Instructor led session (currently planned as Blended Training).
You could earn Cadence Certification after finishing this course, and promote your expertise on social media channels like LinkedIn and Twitter.
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On behalf of the Cadence Learning and Support team
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