Voltus^TM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow. The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.

“Genius is making complex ideas simple, not making simple ideas complex.”
-Albert Einstein

The ever-rising demand for performance and functionality in electronic systems has augmented the complexity of our System-on-Chip (SoC) designs like never before. Improved IC design development capabilities are crucial to meet competitive power, performance, and area (PPA) targets, and deliver faster and predictable design closure. Voltus has adapted to this aggressive pace of designing next-generation ICs by effectively handling the complexity and scalability of such chips with its new cloud-ready XP (Extremely Parallel) solution. Now that we have computational expertise and capacity already taken care of, setting up the Voltus Electrostatic Discharge (ESD) Analysis flow should be a piece of cake. In the first blog of the Demystifying ESD series, we discussed the importance of ESD verification for the reliability of ICs and the key differentiators of the Voltus ESD Analysis solution. This blog post explains how to perform full-chip ESD Analysis in 4 simple steps.

The analysis results are available in real time, so engineers can quickly verify the ESD architecture and design robustness. Here are the detailed instructions for each step:

Step 1: Gather Input Collaterals

Before starting the ESD Analysis flow, make sure you have the following inputs:

• Design data (technology and cell LEFs, top and block-level DEFs) – The LEF and DEF files contain information about the physical layout of the design.
• EM technology file – The technology file contains the current density check limits for each metal layer.
• ESD power-grid views (PGV) - The PGVs are essentially pre-processed cell library databases that contain cell geometries and parasitics required for power/IR/ESD analysis. The idea behind this is to reduce the overall time required for the extraction of standard cells and macros that are reused across multiple designs. It is essential to tag the ESD cells in the PGVs because they contain cell pin information and ESD device electrical characteristics like RON/ROFF or IV curves required to perform non-linear ESD analysis.

Step 2: Prepare a Rule File 

ESD Rule file is a text file that enables designers to specify the requirements for computing effective resistance checks, current density analysis, and connectivity checks.  All the rules can be given at one go in a single rule file.

Following are some of the rule file parameters to customize the flow:

• Rule name - Helps distinguish different flow setups.
• Rule type – Defines the type of analysis to be performed, such as clamp-to-clamp, bump-to-clamp, bump-to-bump, electromigration, connectivity, and so on.
• Net/Bump names – Specifies the nets and bumps to be analyzed or excluded in a specific rule.
• ESD cell types - Specifies the ESD cells/cell types to be analyzed or excluded in a specific rule. Different types of ESD cell information, such as DIODE or CLAMP, RON or ROFF resistance information, and  IV curve are stored in the  PGVs. 
• Resistance threshold – Gives a value that defines the pass/fail criteria.

Here is a sample ESD rule file to check bump-to-clamp resistance:

rule b2c_rule2
type bump2clamp
power -nets all
ground -nets all
reff_threshold 0.5
end rule

Step 3: Run ESD Analysis

ESD analysis can be performed before or after an IR analysis. To run ESD analysis, the “analyze_esd_network”  command must be specified. The objective here is to:

• Identify the violations caused by high effective resistance
• Determine if the current density is above the specified threshold value
• Perform isolation checks indicating isolated bumps that need to be protected, or isolated ESD devices that are to be utilized or excluded from the design

By default, the tool shorts all pin nodes of the lowest ESD cell pin layer and performs the effective resistance checks to the shorted node on the lowest layer. We can customize the pin layer to be shorted by using the clamp_pin_short_file option.

Pro Tip: In scenarios where ESD cells are connected to the PG grid at higher layers, you can specify the layers that are to be dropped from analysis. This is very useful for the designs where the impact of lower PG layers is very small on effective resistance calculation and current density checks. The feature helps in reducing the overall run time involved in PG grid extraction.

Step 4: Analyze ESD Results

The ESD Analysis flow creates the ESD directory that contains a summary report as well as detailed reports for each rule and current density results. The summary report provides an overall view of the ESD impact on the design and gives the PASS/FAIL status for each rule. Based on this report, you can further dive into the detailed report of a specific rule of interest. 

The following snapshot of the summary report illustrates sample ESD checks in the report:

By following these four steps, the analysis will provide full-chip ESD protection of devices and generate a reliable design for the advanced-node processes on your billion-gate designs. This ESD analysis is a user-friendly solution that will surely be a gateway for your design experiments in complex electronic circuitry.

Stay tuned for the next post where we will cover the different types of ESD checks.

Vijetha K Singh

Related Resources

 Performing Electrostatic Discharge Analysis in Voltus

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About Voltus Voice

“Voltus Voice” showcases our product capabilities and features, and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.

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