Voltus^TM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow. The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.

Many of our high-tech gadgets are endowed with numerous features that we sometimes disregard or even forget about. Out of paucity of time or sheer laziness, we often run the washing machine on just two or three programs and rarely try out the other fifteen odd programs that the manufacturer provided. Or we end up using that smart Bluetooth speaker only for listening to music, although it can help make and receive calls, perform household automation tasks, and even provide critical reminders to reduce the stress on our memory. All these potential task-solvers simply remain dormant until a friend comes up with a reminder and a neat demo. That’s precisely what this blog aims to do: brush up on some of the useful features that Voltus has hidden up its sleeve that you probably never got around to trying out.

Here are some very efficient features that Voltus engineers have designed that you might want to deploy:

Hybrid or Mixed Mode Power (Vector-Based and Vectorless) Analysis

Traditionally, dynamic power analysis flows uses either the vector-driven or vectorless approach to identify the instances that are switching and when they switch. However, in most cases, not all blocks have vectors available at the same time or vectors available with high coverage. In this situation, the mixed-mode methodology can be adopted to combine the vector-based and state-propagation-based vectorless dynamic analysis in a single run.

This flow will ensure that there is enough design coverage for quickly identifying potential design weaknesses, reflecting the true distribution of the power inside the block.

Command:
set_power_analysis_mode –method dynamic_mixed_mode

Noise Margin Calculation

In today's nanotechnology era, the power supply noise margin is an important consideration for IC design because noise is a key reliability indicator for semiconductors. Therefore, it is imperative to apply design practices that accurately capture the noise margin or the allowable noise voltage on the input of a gate so that the output is not affected. Voltus uses the Effective Instance Voltage method for the noise margin calculation. In this method, noise margins are calculated with the worst voltages seen on the driver-receiver pins. Noise margins will be calculated for only the driver-receiver pairs where the flop is a receiver, as shown below:

This method uses the elapsed worst-case voltages on the power and ground pins of the driver and receiver instances. The implementation of this design technique to analyze and mitigate noise can benefit designers working on diverse power-grid design styles.

Command:
calculate_noise_margin

Power Density Aware Vector Profiling

With power densities intensifying rapidly as technology nodes are shrinking, there is an ever-increasing demand for developing innovative cooling techniques. Power-density aware vector profiling considers the core regions of high-power density that could produce high dynamic switching current and IR drop. This solution identifies the “hot spots” on the chip early on, preventing chip-performance degradation. 

Command:
set_power_analysis_mode -vector_profile_mode {power_density}

Scan Mode Analysis

Scan-based testing is performed to detect potential manufacturing faults in a circuit, helping to verify the reliability of the physical chip. Scan chains in the design are highly recommended, especially early in the design lifecycle, while defects could still be comparatively high. Voltus offers two models for scan mode analysis, depending on the input provided by the design team:

• Scan shift mode - provides the initial state of all scan flops and the scan-chain order.
• Vectorless mode - provides the scan-chain order and % activity to generate scan pattern based on activity.

Command:
set_power_analysis_mode -scan_control_file

Thermal Model Generation
Last, but not least is the temperature-aware power analysis. This has proven to be among the most invaluable feature for designing your chips to brave thermal conditions. Voltus allows you to perform electro-thermal co-analysis of a single or multiple ICs in a full system environment, where IC, package, heatsink, fan, and the board can be simulated together. In this flow, Voltus generates a thermal model that contains the necessary physical parameters such as power distribution, material properties, and metal density at different layers inside the chip. The Voltus thermal model is then passed on to Celsius to generate a temperature map across the chip. This temperature map is then read back into Voltus to perform thermal-aware signoff.

Command:
report_power -thermal_power_map_file

So, what are you waiting for? Stimulate your inner geek and discover the cool things in Voltus—use it like a pro and unlock the full potential of your design!

Related Resources

Product Manuals	Voltus IC Power Integrity Solution User Guide
Blogs	Voltus Voice: Power Signoff Ramp-Up RAKs – Hello Electrical, Meet Thermal!
Articles	Scan analysis: Recommended setup for scan power analysis FAQ: Common questions related to the scan chain flow in Voltus Dynamic Power Analysis: Recommendation to set up Dynamic Power Analysis flow Recommendation to implement the Vector Profiling flow

For more information on Cadence digital design and signoff products and services, visit www.cadence.com/go/voltushs.

About Voltus Voice

“Voltus Voice” showcases our product capabilities and features, and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.

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