Voltus^TM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow. The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs. Stay tuned for our monthly posts on every third Wednesday.    

If you are a fitness enthusiast, you would have certainly invested in a wearable activity tracker to get off the couch and reach your fitness goals. Not so long ago, these trackers were limited to counting your footsteps. Fast forward to 2020 and we find that the wrist-watch has been rendered obsolete by advanced electronic wrist-bands that track every aspect of your daily physical activity. These devices have a wide range of integrated sensors to accurately measure steps taken, distance covered, altitude attained, heart rate, calories burnt, and even sleep quality to efficiently assist users to improve their health and fitness. This evolution—from a simple pedometer to a complex blend of sophisticated sensors (GPS, gyroscope, oximeter, and so on) coupled with a variety of output signals (haptic feedback, beeps, and multicolor LED displays) in a compact and power efficient form—reminds us of the importance of considering numerous physiological criteria to be able to effectively adopt the optimal exercise and dietary regimen for an individual.

Evolving Technologies: From Isolated Analysis to Co-Analysis

Apart from the fact that these trackers rely heavily on semiconductor technology, the evolution of activity trackers is analogous to that of 3D-IC packaging. With the progressive miniaturization of process nodes, several physical phenomena interact with each other and affect the chip design when stacking multiple die into one package. Among the many factors, we can say that temperature and power are two important characteristics that are closely intertwined, having tremendous impact on the system-level performance and reliability. To give an example of a typical thermal issue in the design process, with an increase in temperature, the leakage power of devices increases, causing more current to flow through metal resistors and rendering the devices susceptible to high IR drop and functional failure.

The legacy standalone solutions for electrical and thermal analysis of 3D designs consider the whole chip to be operating at a single temperature. Such an analysis results in reduced accuracy of temperature distribution across the chip. Consequently, multiple convergence iterations are required to accommodate all the temperature corners and identify the resultant IR drop/electromigration (EM) hotspots.

To overcome these challenges, what we need are the following:

• An electrical solution that reads in the precise temperature gradient across the chip and processes it, resulting in a more accurate prediction of EM and IR drop.
• A thermal solution that provides the thermal profile of the chip, thereby predicting precise temperature distribution at the system-level.
• An integration of these two solutions to exchange electrical and thermal information back and forth.

That’s where our electrical-thermal co-simulation solution comes in.

A Comprehensive and Integrated Solution for Electro-Thermal Co-Analysis

As part of our Intelligent Design Strategy, the Cadence^® Celsius^TM Thermal Solver in conjunction with Voltus^TM IC Power Integrity Solution allows you to perform electro-thermal co-analysis of a single or multiple ICs in a full system environment, where IC, package, heatsink, fan and board can be simulated together.

The following diagram illustrates how iterations happen back and forth between Voltus and Celsius:

This integrated solution increases accuracy in power integrity analysis and enables the results to converge faster. Moreover, it is optimized for cloud environments, featuring a massively parallel architecture that delivers up to 10X cycle time improvements and unlimited scalability.

Interested to learn more about this technology? Let us show you how.

We have created a rapid adoption kit (RAK) that contains scripts and flows, so you can get an accelerated start on achieving accurate co-analysis of a power-grid network on a chip-package-PCB system. This RAK has the following three labs:

• Lab 1 specifies how to run temperature-aware power analysis in Voltus to generate a layer-based ‘Thermal Model’ that contains information about the power generated across the surface of the chip.
• Lab 2 specifies how to import this ‘Thermal Model’ in Celsius and associate it with package, heatsink and board to run the three-dimensional thermal simulation and to generate a temperature map across the chip.
• Lab 3 specifies how to import this temperature map in Voltus and re-run power, IR drop, and EM analysis with the correct operating temperatures for each hotspot region on the chip.

Just as activity trackers enable you to find the optimal fitness regime without burnout, this solution brings thermal analysis and electrical analysis together to quickly simulate and optimize your designs.

Click the following links to access the 3 labs of the Voltus-Celsius Static Electrical Thermal Analysis RAK:

• Lab 1: Thermal Model Generation using Voltus
• Lab 2: Thermal Map Generation using Celsius
• Lab 3: Thermal-Aware EMIR Analysis using Voltus

Related Topics:

• Challenges of On-Chip Thermal Analysis in Electronic System Designs
• Electrical and Thermal Analysis Together
• Celsius and Voltus: 2+2=5

About Voltus Voice

“Voltus Voice” showcases our product capabilities and features, and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.

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- Team Voltus