Voltus^TM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow. The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.

In the first two parts of our series, we presented a walkthrough of the Voltus Extreme Modeling (XM) solution to cut compute resource requirements for extremely large designs, and the three simple steps to create reduced power-grid (xPGV) models. In this post, we’ll explore what it means to use these reduced xPGV models at the top level to lessen detailed analysis effort in the final stages.

To keep the design process as efficient as possible, it is imperative to avoid repeating tasks that waste energy resources and precious time. A smart design analysis is one that can selectively analyze those blocks that need going over, while ignoring blocks that have already been analyzed. However, the resulting final solution needs to be signoff accurate with comparable results as a full-flat analysis. Our technology gives the design engineer the flexibility to deploy hierarchical analysis at certain blocks thereby rendering the analysis highly efficient.

Weaving xPGV Models and DEF Together for Peak Results

Once you have one or more hierarchical blocks analyzed for EM and IR to satisfaction and implemented xPGV generation, the next step is xPGV utilization. The primary objective of this stage is to specify the list of hierarchical blocks you want to replace with xPGVs and the ones you want to analyze flat. You may want all the blocks replaced with an xPGV, in which case the setup is simple. Alternatively, you may want to use xPGV for the largest or most repetitive blocks. For this process, you need to create a control file (flatten_xpgv_block_instances) for both power and rail analysis.

The control file includes a list of block instances that use DEF instead of xPGV for power and rail analysis - that is, specify the instances that are not to be used as xPGV. You can specify a few instances of the same block that will use DEF, and the others that will use xPGV at the top level.

Example:

For a design with three blocks, if you want to use the DEF and xPGV as follows:

Block_1 -> A1 (xPGV) & A2 (DEF)

Block_2 -> B1 & B2 (xPGV for both instances)

Block_3 -> C1 & C2 (DEF for both instances)

Then the control file should contain the following information:

#<instance_name/cell_name> <block_instance_name|All|None>

Block_1 A2

Block_2 None

Block_3 All

 Modeling Large Designs Is Not a One-Size-Fits-All Solution

The Voltus-XM solution provides SoC designers with the flexibility to adapt to their requirements by supporting both the “bottom-up" and "top-down" approach.

The bottom-up approach first generates the xPGV power-grid library from the rail analysis data, which is then used in the top-level electromigration-IR drop (EM-IR) analysis. If the top-level IR drop violations inside the xPGV block need further investigation, you can adopt the top-down approach wherein you can debug the IR drop problem at the block-level by re-simulating it with the top-level block boundary voltages (bbv). The top-down approach runs the top-level analysis, generates block-level boundary voltages and then runs block-level analysis with these boundary voltages. The top-down approach utilizes the actual block boundary voltages instead of ideal voltages. The bbv files will put a voltage source on every node in the block from highest to lowest layers that were found in the xPGV. IR drop on layers below the lowest voltage source will be computed from that point. The resultant IR drop analysis will provide an easier debug of the IR drop problem that occurred at the top level.

So How Does this Flow Work in Practice

In the Tcl script, specify the design loading (top-level design data), power analysis, and rail analysis commands. A snippet of the top-level power and rail analysis commands is as follows:

set_power_analysis_mode \
  …
  -power_grid_library {<path>/All_merge.cl  ../xpgv/hier_block/hier_block.cl}
  -flatten_xpgv_block_instances use_def.txt
report_power …
set_rail_analysis_mode \
  …
  -power_grid_library {<path>/All_merge.cl <path>/xpgv/hier_block/hier_block.cl} \
  -flatten_xpgv_block_instances use_def.txt
analyze_rail …


Here,

• -power_grid_library specifies to use the generated xPGV library and other PGV libraries being used in the flow.
• -flatten_xpgv_block_instances specifies the instances that are to be used as xPGV and DEF.

A Case Study

The following diagram shows ~3.5X improvement in rail analysis runtime using the xPGV flow compared to the flat run with limited accuracy tradeoff:

Key Takeaway

Voltus-XM can play a significant role in addressing the EM-IR analysis challenges on full chip design. This solution offers a significant speedup in the runtime over full flat analysis, process efficiency that mega-sized chips demand, and acceleration of the design cycle.

Related Resources

For more information on Cadence digital design and signoff products and services, visit www.cadence.com/go/voltushs.

About Voltus Voice

“Voltus Voice” showcases our product capabilities and features and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.

Click Subscribe to visit the Subscription box at the top of the page in which you can submit your email address to receive notifications about our latest Voltus Voice posts.