Voltus Voice: Early Power and Thermal Integrity Analysis in 3D-ICs - Why it Really Matters?

Voltus^TM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow. The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.

We are excited to announce that CadenceTECHTALK webinar is back with its session on one of the hottest topics of the day―“3D-IC Chip-Centric Power and Thermal Integrity with High-Performance Hierarchical Analysis”.

What’s the Webinar About?

Advanced packaging technologies are driving semiconductor innovation across vertical markets spanning automotive, aerospace, and 5G systems among others. They offer unique power, performance, and form factor advantages for applications like mobile computing, high-performance computing (HPC), and artificial intelligence (AI). Designers are now able to develop complex system-level designs by integrating homogeneous and heterogeneous dies or chiplets, such as logic, memory, analog, and RF, all into a single design.

But, all these advantages of 3D-ICs don't come without hurdles. There are a few hindrances when transitioning from a single SoC to a multi-chiplet design, and early pre-layout thermal analysis is one of them. A 3D-IC system includes package, interposer, multiple chiplets, through-silicon vias (TSVs), and through-dielectric vias (TDVs). When it comes to supplying power to the chiplets and dissipating heat through various 3D-IC components, power integrity (PI) and thermal integrity pose a major challenge. Since changing the die stack at a later stage in the design cycle is incredibly challenging or sometimes impossible, early analysis is extremely critical in 3D-ICs.

An effective packaging system solution will capture the top-level design intent upfront, and support early exploration of power and thermal issues. In this webinar, we'll take you through a chip-centric perspective on performing PI and thermal integrity analysis in 3D-ICs from early planning to signoff.

The talk will cover the following:

• 3D-IC power grid planning and PI analysis 
• 3D-IC early thermal integrity analysis
• 3D-IC chip-centric power integrity signoff with high-performance hierarchical analysis
• Building chip models for 3D-IC system-level power and thermal integrity

Featured Products: Cadence^® Integrity^TM 3D-IC, Voltus^TM IC Power Integrity Solution, and Celsius^TM Thermal Solver

Date and Time:

March 23, 2022
EMEA: 9:00 GMT / 10:00 CET / 11:00 EET and Israel / 14:30 IST
North America: 10:00am PT | 1:00pm ET

We look forward to seeing you at the webinar. Register now.

Related Resources

For more information on Cadence digital design and signoff products and services, visit www.cadence.com/go/voltushs.

About Voltus Voice

“Voltus Voice” showcases our product capabilities and features, and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.