Voltus^TM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow. The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.

Just as an almanac explores important events of a calendar year and helps you plan next year’s projects, this blog will be a ready reckoner of the highlights in the Voltus blogging space through 2021. Each blog post chimes with innovative strategies for engineers dealing with next-generation products and challenging PPA goals – whether exploring a technique for the right design trade-offs or tackling turnaround time issues when handling large designs.

Here’s the list of diverse topics our blogging series dwelled upon in 2021:

Achieving an optimal trade-off between power and performance targets of battery-operated devices

Providing more functionality with less power and extended stay-on capacity are key to battery-fueled devices. That's why we included the blog post on the rush current analysis flow that helps you to reduce leakage power consumption by controlling the rush current.

Designing chips with better resistance to electrostatic discharge events

ESD is one of the most challenging reliability pain points for IC designers. To address this, we introduced a mini-blog series ‘Demystifying ESD’ that takes you through a range of topics and best practices on how to design for ESD protection.

Unleashing the power of intelligent system design strategy

We had an exclusive conversation with Rajat Chaudhary, Product Management Director of Voltus, and discussed a range of topics from integration with a full suite of design implementation and signoff tools, exciting features of 2021, and future of EM-IR analysis.

Improving the reliability of power grids before the signoff stage

When designing power grids, one question we often ask is have we met the effective resistance goals to sign off power grid implementation early in the design cycle. In the Full-Chip Resistance Analysis blog, we discuss different types of resistance analysis techniques that can be considered to model a robust power grid.

Accelerating hierarchical power integrity analysis and signoff in extremely large designs

As designs evolve in size and complexity, engineers need to ensure their power integrity analysis strategies keep up. In the 'Hierarchical Power Integrity Analysis' mini-blog series, we present the Voltus Extreme Modeling (XM) technology that provides fast, accurate, and memory efficient analysis for large AI and hyperscale designs.

Delivering a streamlined synthesis-to-signoff flow for high-quality digital full-flow implementation

We’ve pulled together 6 migrations tips that will help you transition seamlessly from Voltus Legacy to next-gen Stylus UI, a unified solution for designers working on multiple Cadence tools (Genus^TM, Innovus^TM, Voltus^TM, and Tempus^TM) with shared functionality.

Getting contextual answers to ESD analysis queries

We launched a new tool called ESD Analysis Task Assistant to help designers quickly find ESD-related information. This is especially useful at the “getting started” phase regardless of whether you are running the tool from the command-line interface or graphical user interface mode. The blog gives an overview of the task assistant and outlines how this innovative tool can provide valuable tips to jump-start your analysis.

As we end the year with our version of “Voltus Almanac 2021," rest assured that we will continue to share insights on our intelligent system design strategy to achieve signoff power integrity.

Related Resources

Product Manuals	Voltus IC Power Integrity Solution User Guide Voltus IC Power Integrity Solution Text Command Reference
Video	What's New In Voltus IC Power Integrity Solution - SSV21.1 What's New in Voltus IC Power Integrity Solution - SSV 21.11 Voltus ESD Analysis: Task Assistant

For more information on Cadence digital design and signoff products and services, visit www.cadence.com/go/voltushs.

Contact Us

For any questions, general feedback, or even if you want to suggest a future blog topic, write to voltus_blogs@cadence.com.

About Voltus Voice

“Voltus Voice” showcases our product capabilities and features, and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.