Voltus^TM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow. The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.

Massively parallel execution, hierarchical power integrity analysis, digital full flow, and system analysis are all key aspects of power signoff. In this interview with Rajat Chaudhry, Product Management Director of Voltus, we discuss the power signoff strategies to accelerate delivery of advanced technologies, our product innovations that address key design challenges, his views about the future of EM-IR, and much more.

So let’s start!

Q. Hello Rajat, could you let us know about your professional journey in the semiconductor industry, and how you became part of the Voltus team?

Rajat: I started my career as a developer in the EDA domain in late 90s at Motorola Semiconductor Products Sector, which later became Freescale and is now part of NXP. While there, I’d worked on developing an in-house EM-IR analysis tool at a time when EM-IR started becoming a major concern in chip design. Then, I moved to IBM and worked on developing an in-house Power Analysis tool for the Cell processor, which was used in PlayStation®3. After that, I served with LSI Corporation (now Broadcom) where I worked on low power design methodology and hardware power characterization. I joined Cadence about five years back in the Voltus product engineering team, working closely with some of our key customers. For a year I was given the responsibility of managing the Celsius^TM Thermal Solver product engineering team and then rejoined Voltus in a product management role last year. So, overall, my career has revolved around EM-IR signoff, power, and thermal analysis.

Q. If you were to pick up the one thing that gives Voltus its competitive edge in the electronics design world, what would it be?

Rajat: I think our greatest strength is the fact that Voltus is integrated with a complete portfolio of full-flow digital and signoff products and system analysis tools offered by Cadence. Along with the Cadence® Virtuoso® and Innovus^TM Implementation System design platforms, Voltus is a part of an efficient signoff ecosystem that provides a seamless design flow all the way from Place & Route (P&R) implementation to timing and power analysis. We believe that this streamlined and co-design flow enhances productivity throughout the design cycle. In addition, considering its distributed architecture, best-in-class solvers, and an amazing R&D team, Voltus offers the best solution for complex and cutting-edge designs. 

Q. Can you elaborate further on how the integration of Voltus with our full-flow digital and signoff products helps in achieving better results and first-pass silicon success?

Rajat: Voltus offers a unified design environment with Innovus^TM Implementation System and Tempus^TM Timing Signoff Solution, facilitating fast and seamless IR drop-aware implementation and timing signoff. In the Innovus IR drop-aware implementation flow, which we call Innovus Power Integrity (Innovus PI), you can now account for IR analysis information for your designs as part of the implementation process. This way you don’t run into any big or inconvenient surprises at the time of signoff. The critical steps included in Innovus PI are:

- IR-aware placement

- IR-aware clock tree synthesis (CTS)

- PG addition and trimming

- Intelligent PG fill with Pegasus^TM

- IR drop fixing with Tempus ECO

Likewise, Voltus is integrated with Tempus as part of the Tempus Power Integrity (Tempus PI) flow. One of the biggest challenges in EM-IR analysis is design coverage; in other words, identifying the switching activity in your design that can cause timing violations due to voltage drop, resulting in silicon failure. This is a very complex problem because the possibility of locating the specific IR-induced timing violations is almost infinite. To address this, Tempus PI uses IR and timing sensitivity data from Voltus and Tempus to intelligently create vectors that can cause IR-driven timing failures. Tempus PI can certainly help sign off the highest performing designs while avoiding costly silicon re-spins, especially at advanced nodes.   

       
Q. What do you think have been the top achievements of Voltus in the past three years?

Rajat: There are many achievements to name, the biggest being the complete deployment of our fully distributed Voltus XP architecture at all stages of the flow--design parsing, extraction, power analysis, rail analysis, and GUI. With the advent of AI and hyperscale designs about four or five years back, we started hearing from our customers about the very large designs they were envisioning. We realized that to sign off these designs, it was imperative for us to re-architect many parts of the tool to make it seamlessly scalable for addressing performance and capacity requirements. Our R&D took on that challenge and was able to deliver the new architecture in time for our customers to analyze their giga-scale designs. Within the last three years, Voltus XP has fully matured and is now the standard use model for most of our customers. Voltus XP has already been used to sign off many designs at advanced N5 and N7 nodes, ranging from 100s of millions of cells to billions of cells.

Another major feature has been our Voltus XM hierarchical analysis solution that complements our fully flat distributed capability. Voltus XM lets you build compact models of IP, which, in turn, help you perform faster analysis with a lot less memory. I think a breakthrough in accuracy was the major turning point in the development of this technology. We are seeing very good correlation with the fully flat analysis even with the inclusion of package models. Last but not the least, the improvements we have made in our electrostatic discharge (ESD) solution, both in analysis and GUI, have proven to be significant advancements towards optimal ESD protection for IC designs. We have a comprehensive list of ESD checks available in Voltus ESD. I am very confident that Voltus ESD is the fastest full-chip ESD analysis feature in the market. Some of our customer benchmarks show a significant performance gain over other competitive solutions.

Q. How is Voltus contributing to the overarching systems design strategy of Cadence?

Rajat: Robust power delivery network is a critical part of any system. In the past, we had mainly focused on analyzing the on-chip power delivery network, including package models for transient analysis. Now, we are starting to see a lot more interest in heterogeneous packaging technologies from our customers to design multi-die systems. Accurate EM-IR signoff requires analyzing multiple dies together while preserving accurate models for the interconnects and the package.
Voltus is a key component of the Cadence Multiphysics System Analysis solution and can be used in conjunction with Celsius Thermal Solver, Clarity^TM 3D Solver, and Sigrity^TM technologies. This high-level integration enables our engineers to perform system-level power integrity analysis and design closure. We now have customers who wish to include board-level models as part of chip power sign off. From a system vantage point, Voltus provides accurate chip models for our Sigrity system analysis tools. Another important area in system design is thermal analysis, especially that of 3D-ICs. In most electronic systems, chips are the main source of heat generation. Voltus plays a critical role here by generating chip thermal models for Celsius Thermal Solver that can be used for chip or full system thermal analysis. So yes, Voltus is surely an integral part of the Cadence Intelligent System Design^TM strategy, enabling our customers to accurately address EM and thermal issues across chip, package, PCB, and enclosure.

Q.  What are some of the biggest challenges when performing power integrity analysis at the chip-package-board levels, and how does Voltus address them?

Rajat: I think the biggest challenges in performing power integrity analysis at the chip-package-board levels are the ability to analyze very large designs, extraction, and integration of accurate package and board models in the analysis.
Voltus offers a fully distributed architecture that delivers unprecedented performance and capacity. For package or board model extraction and integration, when Voltus is used in conjunction with Sigrity and Clarity tools that are designed to handle very large designs, our users are empowered to perform seamless co-analysis of system-level designs.

Q. What features are you most excited about in 2021?

Rajat: I am very excited about the following features in 2021:

- Voltus XM Hierarchical Analysis: Our customers will be able to use this methodology to improve the performance and memory requirements for their runs. The big breakthrough here is being able to generate a context-independent model and still achieve very good accuracy.

- Voltus-ESD: I think the performance and new features that we have added to Voltus ESD in 2021 will make it shine this year. We are also working closely with foundries to generate ESD rules for Voltus.

- Multi-Die Analysis: We are seeing more activity in this area, and I am excited to work with our customers to solve their challenges and look at emerging innovations.

Q. What do you see as the future of EM-IR analysis?

Rajat: With the increasing demand for end-to-end solutions across chips, IP, packages, PCBs, and systems to meet the challenging design requirements, firstly, I see a progressive shift towards including more system-level components in power signoff. Second is the emergence of multi-die integration and signoff to support advanced packaging technologies for next-gen designs, prompting us to keep pace with varying modelling requirements for these technologies. Third is the improvement of performance and capacity of EM-IR signoff tools as design sizes continue to grow in form and complexity. Fourth is the increased usage of AI technologies in IR-aware design implementation, providing a scalable solution to reduce design iterations and faster convergence.

Q. What activities do you enjoy when you are not working on EDA innovations? Tell us something about your hobbies and interests.

Rajat: When not working I enjoy activities like hiking and biking on nature trails. I am also an avid tennis player and try to play at least on the weekends. I enjoy reading non-fiction books especially related to economics, finance, and philosophy.

Thank you Rajat, for sharing your views on the latest trends in the system-on-design (SoC) landscape and we look forward to getting more insights from you on future innovations in Voltus.
-- Priya E. Joseph

Related Resources

• Hierarchical PI Analysis of Large Designs with Voltus Solution (Webinar)
• Demystifying ESD—Charting Your Way through Voltus ESD Reports
• Amplifying Your Chip Performance and Reliability to Solve Big-Data Challenges
• Accelerate Power Signoff and Design Closure with Targeted Local PG Addition
• Tempus Power Integrity Solution - Find Those Needles in the Haystack Quickly!

For more information on Cadence digital design and signoff products and services, visit www.cadence.com/go/voltushs.

About Voltus Voice

“Voltus Voice” showcases our product capabilities and features, and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.

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