Voltus^TM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow. The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.

Today’s commercial aircraft are marvels of aviation technologies. We joke about pilots sitting idly in the cockpit while the ‘fly-by-wire’ system takes control of the flying. But that is far from the truth: the captain and co-pilot are still very much in charge, taking the crucial decisions that keep the flight on path. There is a massive amount of data that pilots must quickly analyze and filter to decide on each maneuver—monitoring of altitude, engine power, wing flaps, wind-speed, turbulence, and air pressure— they make during the flight, apart from frequent communication with Air Traffic Control (ATC). Although advanced measurement devices capture multiple data and transmit them onto easy-to-read multicolor displays, the captain must continuously observe these changing parameters while being fed critical information by the co-pilot.

The pilot’s situation mirrors that of the design engineer who is also required to filter and analyze big data swiftly for selection of the optimal design. The co-pilot’s narration of the various parameters and the myriad values on display are analogous to the reports that the engineer uses to eventually chart out the electrostatic discharge (ESD)-safe and most effective path for the IC chip.

It is quite apparent that an effective ESD analysis depends squarely on the quality of reports. It is the efficient reporting and visualization in Voltus ESD that give designers a comprehensive overview and the ability to locate pertinent details. This leads to faster analysis and debugging of ESD issues to avoid chip failure. In this concluding blog of the “Demystifying ESD” series, we talk about how to read the Voltus ESD analysis reports and utilize its GUI features to gain a clear insight on ESD needs from the early-design phase to tapeout.

The ESD Report feature is designed to help you quickly detect the top violating paths that can cause ESD failures. ESD reports and GUI make it easy to:

• Analyze a variety of resistance checks and possible ESD discharge paths
• Filter and sort the violations caused by high effective resistance
• Visualize the location of the fly-lines between the “from clamps/bumps” and the “to clamps/bumps”
• Support a massively parallel architecture to handle many combinations in bump-clamp pairing for very large designs

Types of Reports Available 

The types of ESD reports generated during Voltus ESD analysis are:

• Summary Report – This report gives a one-stop view of all the specified ESD rules or checks in a single report. The report comprises the PASS/FAIL status per net for each rule and the corresponding rule details. This report allows you to—assess the ESD impact on the total design, identify the rule types and nets that are most vulnerable to ESD events, and identify the bumps/ESD devices that violate the given effective resistance threshold limit. For example, you can use a summary report to showcase the passing and failing paths for the bump-to-clamp (b2c), bump-to-bump (b2b), and clamp-to-clamp (c2c) effective resistance rules at one go.
• Individual Resistance Check Report – This report gives the detailed information for each of the specified rules. Every detailed effective resistance check report includes the bump and clamp information, effective resistance for the paths analyzed, threshold resistance value for the rule, ESD pins, layers, location, and pass/fail status. This information is available for each net analyzed in the design. The net is set to the fail status even if one clamp-to-bump/bump-to-bump/bump-to-clamp path violates the required threshold value.
• Connectivity Check Report – This report provides the information about the number of isolated clamps and bumps with their names.
• Current Density Check Report – This report includes details about the current values through each segment calculated by the tool, current limit value derived from the foundry technology files, segment layer, location, width, Blech length, current density, and other useful information.

How to View Your ESD Reports

The ESD analysis flow generates the ESD directory that contains all the ESD reports. You can view the ESD reports in both the command line interface and the graphical user interface (GUI) mode.

Let’s see how to access and view the ESD results in the Voltus GUI:

1. Choose Power Rail ─ ESD Results to open the ESD Summary window.
2. Browse the ESD directory to load results.
3. Select a specific rule to view its summary.
4. Select a net to see the rule details.
5. Select a row to highlight the flight lines between the “from clamps/bumps” and the “to clamps/bumps” in the layout window. Green flight lines indicate passing paths and red flight lines indicate failing paths.

You can choose to refer to the reports for data mining or load it in GUI to graphically visualize them.

Strategies to use ESD Reports and GUI to the Fullest Potential

Use the following features to rapidly identify and resolve design violations using the reports and the GUI:

• Enhanced Filtering and Sorting Capabilities - Gives you the flexibility to filter and view the effective resistance and pass/fail status of the desired “from bump/clamp” or “to clamp/bump”. In addition, you can sort the report columns in an ascending and descending order. These features allow you to narrow down the large number of bump-clamp pairs and display only the relevant data.
• Ability to Show/Hide Plots – Allows you to selectively turn on the flight lines from a source (clamp or bump) to the sink (clamp or bump). This allows you to view the routing connections of the ESD cell and further debug the area of the design with violations.
• Highlight Least Resistive Path - Shows the least resistive path for a specific bump-to-clamp pair in the GUI. You can also generate the least resistive path report that displays the resistance between each node pair along the path. This helps in faster debug of the failing bump-to-clamp pairs.
• View and Analyze Reports in Innovus - Extends ESD analysis and debugging capabilities for reduced implementation iterations when Voltus is accessed from Innovus^TM Implementation System.

Voltus ESD solution offers an easy way to verify the robustness of the ESD protection scheme for your ICs by reporting ESD susceptible devices and the associated current discharge paths. As the captain of your airship, you can trust these concise and accurate reports generated by your co-pilot and navigator and steer your precious design forward without worrying about the uncertainties at landing.  

-- Vijetha K Singh and Priya E. Joseph

Related Resources

• Demystifying ESD – Touch Ground with a Designer-Centric Protection Scheme
• Demystifying ESD – Four Simple Steps to Run ESD Analysis Full-Chip Flow
• Demystifying ESD – 5 Types of Checks to Bump up Your ESD Protection

For more information on Cadence digital design and signoff products and services, visit www.cadence.com.

About Voltus Voice

“Voltus Voice” showcases our product capabilities and features, and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.

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