Voltus^TM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow. The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.

Legend has it that Benjamin Franklin set up an interesting experiment to investigate the atmospheric phenomenon of lightning. During a storm, he apparently flew a silk kite attached to a thread with a metal key. As he predicted, the kite and the thread got charged by lightning and he "felt" the charge by holding his knuckle to the key and getting a mild shock. By this he deduced that lightning was in fact a form of electricity being transferred from one body to another—what we call static electricity today. Reading about this tale of America’s pioneering scientist makes us wonder why electrostatic discharge hasn't been mastered even 300 years later and how we still need to be innovative to protect our systems from the damaging effects of a sudden static electricity discharge! Preventing such an accident is precisely the aim of the Voltus ESD Analysis solution.

This blog is a continuation to the Demystifying ESD blog series on designing a robust system-on-chip (SoC) by taking steps to add Electrostatic Discharge (ESD) protection into your design flow. When running the Voltus ESD Analysis flow, there are different kinds of checks you can perform to ensure that the total resistance and current density of the ESD discharge paths remain below a given threshold. Read on to find out the various checks that are possible with our tool.

Bump-to-Clamp Check

This check computes the effective resistance from each bump to all the connected clamps/ESD instances or from each clamp/ESD instance to all the connected bumps in the design, or both. It allows you to perform two types of checks, one is the shorted bumps to all clamps and the second is each bump to each clamp.

In the following example, a pass status is given when the effective resistance value for each Bump-to-Clamp pair (R1, R2, R3)  is within the specified resistance threshold:

Clamp-to-Clamp Check

This check computes the effective resistance between all clamps of a specified type to all clamps of another specified type for all the required nets.

In the following example, a pass status is given when the clamp-to-clamp effective resistance (R3 or R2) for the required nets is within the specified resistance threshold.

Bump-to-Bump Check

This check computes the effective resistance between power and ground bumps through all the connected clamps.  This check gives users the flexibility to perform resistance checks on all the bumps for the nets specified or just for the bumps of interest.

In the following example, a pass status is given when the total effective resistance value of the ESD discharge path (R1+R2) is within the specified resistance threshold:

In Multi-Supply Multi-Voltage (MSMV) SoC with multiple domains, the discharge path could enable multiple clamps before draining out.

In the following figure, the discharge path for Bump1 could be Bump1 (VDD) => Clamp A => Clamp B => Bump3 (VSS):

Voltus supports such multi-stage paths that pass through multiple clamps.

ElectroMigration or Current Density Checks

Checks whether the current densities on the wires/vias exceed the foundry-specified limits that cause metal melting or fusion.

Connectivity Checks

Checks if there are any bumps that are not protected by an ESD cell, or checks if there are any clamps that are not connected to any bumps. 

As mentioned in the previous blog “Four Simple Steps to Run ESD Analysis Full-Chip Flow”, the different rule checks can be given in a single rule file, as shown below, that can be customized to the specific needs of the design engineers.

The Voltus ESD Analysis solution can help you easily and accurately report the passing and failing ESD discharge paths and fix the violations caused by high effective resistance or current density along these paths, thereby preventing any ESD accidents in your design.

In the next blog of this series, we explain how to analyze effective resistance and current density results and perform GUI-based debugging.

Priya E. Joseph

Related Resources

• Demystifying ESD – Touch Ground with a Designer-Centric Protection Scheme
• Demystifying ESD – Four Simple Steps to Run ESD Analysis Full-Chip Flow

For more information on Cadence digital design and signoff products and services, visit www.cadence.com.

About Voltus Voice

“Voltus Voice” showcases our product capabilities and features, and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.

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