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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification

Latest blogs

Incisive Software Extensions (ISX) vs Co-Verification Link (CVL)

Team Specman has been doing a great job supplying nifty tech tips and other useful…

• 3 min read
CVL , Co-verification link , System Design and Verification , Specmen , Incisive Software Extensions , ISX

Linking C and e: The Co-Verification Link

[Join Team Specman in welcoming guest blogger Jason Andrews. Jason is a recognized…

• 3 min read
Specman , HW/SW , C , e , ISX , Incisive Enterprise Simulator (IES) , Jason Andrews , IES

"...Yes, Virginia there is a Specman"

I usually try to visit many of our customers in Europe (and other parts of the world…

• 3 min read
SystemVerilog , IntelliGen , Specman , metric driven verification (MDV) , Functional Verification , Open Verification Methodology , OVM , Coverage-Driven Verification , e , coverage driven verification (CDV) , Aspect Oriented Programming , eRM , AOP

Interview With Cadence Verification IP Architect Levent Caglar

Even in these challenging economic times, interest in Verification IP ("VIP") has…

• less than a min read
verification strategy , Functional Verification , VIP , Levent Caglar

Tech Tip: Avoiding "Error! Integer Overflow" With Incisive Simulator

While simulating a VHDL design with Incisive Simulator, if an integer overflow is…

• 1 min read
NCVHDL , Functional Verification , Incisive Enterprise Simulator (IES) , IES

"ClubT" Newsletter Issue #3 Just Posted

Specmaniacs and Other Trailblazers, The latest edition of the 'ClubT ' newsletter…

• less than a min read
IEEE 1647 , SystemVerilog , IntelliGen , Low Power , Specman , HW/SW , verification strategy , Verification methodology , metric driven verification (MDV) , Functional Verification , Cadence VIP portfolio , Testbench simulation , OVM , VIP , OVM e , Coverage-Driven Verification , CDV , Multi-domain verification: HW/SW co-verification , e , Enterprise Manager , Enterprise Planner , ISX (Incisive Software Extensions) , Plan and metrics management , coverage driven verification (CDV) , Aspect Oriented Programming , ISX , System Verification , Incisive Enterprise Simulator (IES) , IES , AOP

Functional Verification More Important than Ever in 2009?

Here in Cadence Product Marketing, we're still recovering from our very busy annual…

• 1 min read
metric driven verification (MDV) , Functional Verification , Formal Analysis , Coverage-Driven Verification , coverage driven verification (CDV) , OVM 2.0

Report On The MDV "Deep Dive" Workshops

As heralded in a prior posts, we recently hosted some "alumni" from our recent Techtorials…

• 6 min read
workshops , verification strategy , Verification methodology , metric driven verification (MDV) , Coverage-Driven Verification , Multi-domain verification: HW/SW co-verification , Enterprise Manager , Enterprise Planner , ISX (Incisive Software Extensions) , Plan and metrics management , coverage driven verification (CDV) , ISX , Incisive Enterprise Simulator (IES) , techtorial

Exploring the Virtual Platform Part 2

This week's installment of the "Exploring the Virtual Platform" series focuses on…

• 5 min read
virtual platform , System Design and Verification , ARM , linux , QEMU

Tech Tip: Managing Specman esv File Size

When compiling e files on top of Specman, or when using the save command, Specman…

• less than a min read
Specman , e , Incisive Enterprise Simulator (IES) , IES

Ride The Economy Slow-Down

Last week, at Cadence Sales Kickoff, we have heard fascinating presentations from…

• less than a min read
System Design and Verification , IP re-use , ASIC/ASSP

VIP Following OVM Frees Users to Choose SystemVerilog and e

Back in November Cadence introduced a vastly expanded verification IP portfolio using…

• 1 min read
SystemVerilog , OVM , VIP , e , multi-language , eRM

New AEware: Generate vr_ad Definitions for IP-XACT XML IP Blocks

[Please welcome guest blogger Steve Hobbs, an Application Engineer in our Field…

• 5 min read
Specman , IP-XACT , vr_ad , Register Package , e , Spirit

Welcome to the "Exploring the Virtual Platform" Series

Today I'm starting a series of articles related to what is commonly called the Virtual…

• 5 min read
virtual platform , System Design and Verification , virtual protoype

Aart DeGeus' Surprise Comment at Last Night's EDAC CEO Forum

Last night the Electronic Design Automation Consortium ("EDAC", the trade group for…

• 2 min read
IEEE 1647 , events , Functional Verification , e , EDAC

Generation Debugging With "IntelliGen" (With Video)

You might have seen the Generation Debugger of Specman's new Generation Engine IntelliGen…

• 3 min read
IntelliGen , Specman , e , Incisive Enterprise Simulator (IES) , IES

Predictions for 2009

Having summarized the main verification technology-specific observations that the…

• 3 min read
Specman , HW/SW , verification strategy , metric driven verification (MDV) , Functional Verification , OSCI , Multi-domain verification: HW/SW co-verification , ISX (Incisive Software Extensions) , SystemC , ISX , System Verification , Incisive Enterprise Simulator (IES) , IES

Functional Coverage for Embedded Software

Hardware verification has evolved into keeping track of a pile of different types…

• 3 min read
FoCus , IBM , System Design and Verification , Specmen , DV club

The New Generation Testcase Utility

Specman's new Generation Engine, "IntelliGen", adopts an entirely new generation…

• 4 min read
IntelliGen , Specman , Functional Verification , Testbench simulation , e , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , IES , AOP

A Look Back On 2008 (Before Hazarding Predictions for 2009)

Before I dare take a stab at adding to the many predictions already made for 2009…

• 4 min read
HW/SW , verification strategy , metric driven verification (MDV) , Functional Verification , Open Verification Methodology , OVM , Coverage-Driven Verification , CDV , Multi-domain verification: HW/SW co-verification , e , Enterprise Manager , Enterprise Planner , coverage driven verification (CDV)

The Eternal Debate: "Like" vs. "When" Inheritance

First: Happy New Year, Specmaniacs! Much like the rivarly between the New York Yankees…

• less than a min read
IEEE 1647 , Specman , verification strategy , Functional Verification , e , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , IES , AOP

Power tool: The Reflection API

One endless source of neat little tricks is the Reflection API built into Specman…

• 1 min read

Metric-Driven Verification in a Box...

In my last few posts, I was explaining our focus here in Cadence Verification on…

• 1 min read
metric driven verification (MDV) , Functional Verification , Open Verification Methodology , Cadence VIP portfolio , OVM , VIP , Coverage-Driven Verification , CDV , e , Verification IP modeling , eRM

Make Your Command Line Life Easier With "specman -e"

Hi All, It always amazes me to see just how many Specman users make use of the interactive…

• 1 min read
Specman , Incisive Enterprise Simulator (IES) , IES

Who said Cadence Can't Invent New Technology Anymore?

I and the rest of the Cadence C-to-Silicon Compiler (CtoS) team were thrilled yesterday…

• 1 min read
deepchip , System Design and Verification , C-to-Silicon

Shout-out: Q1 2009 DV Club Schedule Posted

Last month I had the pleasure of attending a DV Club lunch presentation on analog…

• less than a min read
events , verification strategy , Verification methodology , Functional Verification

Thanks for a Great 2008!

Even though 2008 will probably go down in history as the year of Doom and Gloom we…

• 1 min read

Using e Ports

The other day I saw some posts to the Yahoo Specman group regarding e ports. The…

• 3 min read
IEEE 1647 , Specman , verification strategy , Verification methodology , Testbench simulation , e , Verification IP modeling , eRM , Incisive Enterprise Simulator (IES) , IES
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