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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification

Latest blogs

How To Create L3 Cache Command Overflow Stress Test in Less Than 2 Days

One category of difficult SoC tests to create are stress tests, to validate the limits…

• 4 min read
SoC verification , perspec system verifier , Accellera , pss , portable stimulus

Put On Your Perspectacles: How Perspec Can Speed Up Your Testbench

It’s no secret that the bulk of time running simulations is spent on the testbench…

• 3 min read
Functional Verification , Perspec , xcelium , testbench

Do You Have The Tools You Need To Verify Your ARM Multi-core, Coherent SoC?

Multi-core, coherent SoCs are very complex and verifying their behavior requires…

• 1 min read
SoC verification , perspec system verifier , Accellera , ARM , pss , portable stimulus

Save & Restore with More: Preserve Your Entire SoC

The concept of Save and Restore is simple: instead of re-initializing your simulation…

• 3 min read
Functional Verification , x-team , update , xcelium simulator , feature , productivity , xcelium , save and restore

Infineon’s Coverage-Driven Distribution: Shortcutting the MDV Loop

There are more ways to improve productivity in the verification process than simply…

• 3 min read
Specman , CDD , CDNLive , Infineon , Functional Verification , e language , efficiency , MDV

How to Model State Machines in the Accellera Portable Stimulus Standard for Low Power…

The Accellera Portable Stimulus Standard (PSS) is experiencing growing customer interest…

• less than a min read
Low Power , SoC verification , perspec system verifier , Accellera , pss , portable stimulus

X-Propagation: Xcelium Simulator’s X-prop Technology Ensures Deterministic Reset

All chips need to cold reset on every power-up. Warm resets, however, are a bit more…

• 2 min read
SystemVerilog , Functional Verification , xcelium , Reset , simulation

Moving to Xcelium Simulation? I’m Glad You Asked

Ready to take the next step in simulation technology with a true third-generation…

• 2 min read
performance , Self-Help , uvm , simvision , RAK , Multi-Core , Appnote , troubleshooting , simulation , Cadence support

ROHM CO., Ltd Adopts Our Functional Safety Verification Solution

On July 17, 2017, Cadence announced that the Cadence® Functional Safety Verification…

• less than a min read
functional safety , Functional Verification , ROHM Co. , press release , ISO 26262

Xperiences with Xcelium: Hewett-Packard Enterprise Makes the Switch

At Hewlett-Packard Enterprise (HPE), the team working to create IP for “The Machine…

• 1 min read
Functional Verification , xcelium , hp enterprise

Enum compatibility error in Specman

One of my favorite quotes about SW programming is the following by Edsger Dijkstra…

• 4 min read
enumerator , Specman , Incisive , e language , xcelium , verification

Mediatek Deploys Perspec for SoC Verification of Low Power Management (part 2 of…

Here we go through the application of Cadence Perspec™ System Verifier by Mediatek…

• 1 min read
uvm , Perspec , coherent , perspec system verifier , coherency library , coherency , Accellera , mediatek , ARM , pss , portable stimulus

Mediatek Deploys Perspec for SoC Verification of Low Power Management

Mediatek has been using the Cadence Perspec™ System Verifier for their SoC level…

• 2 min read
uvm , Perspec , coherent , perspec system verifier , coherency library , coherency , Accellera , mediatek , ARM , pss , portable stimulus

Cadence @ DAC: What to Expect and What to See

Cadence returns to DAC 2017 this year, showcasing our full verification suite. Here…

• 3 min read
DAC , methodology , EDA , Formal verification , verification

New VIP for ARM AMBA 5 CHI Issue B

In coordination with the announcement of the new ARM® AMBA® 5 Coherent Hub Interface…

• 3 min read
Verification IP , VIP , AMBA , ARM , CHI VIP

See Perspec Running Accellera Portable Stimulus Examples Here and Now!

Accellera has announced the release of an Early Adopter specification of the Portable…

• less than a min read
SoC verification , perspec system verifier , Accellera , pss , portable stimulus

Accellera Has Done It Again! Portable Stimulus Standard Available For Review

In a press release this morning, Accellera announced availability of an Early Adopter…

• 2 min read
CDNS , Perspec , Accellera , pss , portable stimulus

A Brief Introduction to Xcelium

Welcome to the XTeam blog! We are a team of bloggers dedicated to showcasing the…

• less than a min read
Low Power , digital mixed signal , Functional Verification , Multi-Core , xcelium , parallel simulation

Have You Fully Verified Your Multi-Core, Cache-Coherent SoC? Find Out How we Can…

You might have thought it would be “just another DAC” this year, again in Austin…

• 3 min read
DAC , SoC verification , Perspec , pss , Accellera PSS

SoC Verification with Portable Stimulus Using Perspec System Verifier

This year’s CDNLive San Jose was another gem. Many great keynotes, customer presentations…

• 2 min read
SoC verification , Perspec , perspec system verifier , Qualcomm , portable stimulus

A Seamless Path to the Portable Stimulus Standard

In our last blog post , we reviewed some of the activities at the recent Design and…

• 3 min read
uvm , prototyping , pswg , Acceleration , Functional Verification , Perspec , System Design and Verification , Palladium , SoC , Emulation , Simulation acceleration , DVcon , Accellera , metric-driven verification , Hardware/software co-verification , portable stimulus , simulation , verification

Static Members in e

How do you define elegant or clean code? Usually, you know it when you see it; defining…

• 9 min read
Specman , Incisive , e language , static , xcelium , verification

Specman in Xcelium

Just recently Cadence announced the new superb simulator, Xcelium . Just as Specman…

• 5 min read
IEEE 1647 , funtional verification , Specman , Functional Verification , e , e language , Funcional Verification , specman elite , Incisive Enterprise Simulator (IES) , IES , verification , IES-XL

Portable Stimulus Shines at DVCon

For me, this week was almost entirely consumed with the Design and Verification Conference…

• 4 min read
uvm , prototyping , pswg , Acceleration , Functional Verification , Perspec , System Design and Verification , Palladium , SoC , Emulation , Simulation acceleration , DVcon , Accellera , metric-driven verification , Hardware/software co-verification , portable stimulus , simulation , verification

What Sort of Bugs Does Portable Stimulus Find?

In a recent blog post , we discussed some general concepts of bugs, problems, issues…

• 3 min read
hardware-software co-verification , uvm , Low Power , pswg , debug , Functional Verification , System Design and Verification , embedded software , Emulation , Accellera , Hardware/software co-verification , debugging , portable stimulus , interrupts

Preview of an Exciting DVCon

In the overall world of EDA, the Design Automation Conference ( DAC ) is the biggest…

• 3 min read
uvm , prototyping , pswg , Acceleration , Functional Verification , Perspec , System Design and Verification , Palladium , SoC , Emulation , Simulation acceleration , DVcon , Accellera , metric-driven verification , Hardware/software co-verification , portable stimulus , simulation , verification

IEEE Std 1647™ 2016 - e Language - New Standard Publication

Congratulations to the IEEE-1647 e Functional Verification Language Working Group…

• 2 min read
IEEE 1647 , Specman , e , e language , specman elite

Bare Metal Tests and Hardware-Software Co-Verification

One interesting question that arises from time to time is whether the Cadence® Perspec…

• 4 min read
hardware-software co-verification , uvm , pswg , Acceleration , Perspec , virtual platform , System Design and Verification , Emulation , System simulation and analysis , Accellera , FPGA prototypes , testbench , portable stimulus , silicon , bare metal , verification
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