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Current verification techniques cannot keep pace with the growing arithmetic nature of today´s designs.
With the advent of AI, cryptography, and other emerging domains, the amount of datapath in designs today is growing exponentially. These datapath designs typically involve arithmetic units doing integer, fixed-point, and floating-point operations for matrix multiplications, polynomial computations, FFTs, and many other complex arithmetic functions.
Simulation is severely inadequate to verify such designs because of the sheer number of possible input combinations. Furthermore, arithmetic blocks have been traditionally intractable for formal tools.
Cadence® Design Systems brings to you an advanced formal tool, Jasper C2RTL App, which provides a significant productivity boost to verify such datapath circuits.
Join Cadence Training and Product Engineering Architect Vaibhav Mittal for this free, one-hour live webinar.
In this webinar, you’ll learn about:
The webinar presentation will be followed by a live Q&A session with Vaibhav Mittal.
Date and TimeTuesday, April 5
08:30 PDT / 11:30 EDT / 16:30 BST / 17:30 CEST / 18:30 IDT/ 21:00 IST (India)
To register for the “Embracing Datapath Verification with Jasper C2RTL App” webinar, use the REGISTER button below and sign in with your Cadence Support account (email ID and password) to login to the Learning and Support System. Then select “Enroll” to register for the session. Once registered, you’ll receive a confirmation email containing all login details.
If you don’t have a Cadence Support account, go to Registration Help or Register Now, and complete the requested information.
You might also be interested in our Jasper University and how to earn Cadence Digital Badges.
For questions and inquiries, or issues with registration, reach out to us:
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