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The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer rate with PAM4 (Pulse Amplitude Modulation with 4 levels) modulation and uses FLIT (Flow Control Unit) as the unit of communication for efficiency. In ‘What Disruptive Changes to Expect from PCI Express Gen 6.0? we covered what significant features PCIe 6.0 evolved to embrace.
Amongst many new features and changes in PCIe 6.0, we will talk about one major significant new feature: L0p. The following mainly touches upon challenges and corresponding solutions based on our design and verification experiences. For more relevant PCIe 6.0 verification challenges, see Unraveling PCIe 6.0 FLIT Mode Challenges and Unraveling PCIe 6.0 Training Sequences Update and Verification Challenges.
L0p in PCIe 6.0
With the increase of demand for power consumption scaling with bandwidth usage without impacting traffic flow, the new L0p state is introduced in PCIe 6.0. Meanwhile, L0s is not supported in FLIT mode (L0s is less robust and less effective and does not support retimes, etc.). L0p is optional for link width resizing and is used in FLIT mode only.
The existing dynamic link width change can change the link, but it will lose several microseconds to do the state transition. L0p is symmetric in terms of the same width in both directions. It maintains at least one active lane during the width change to ensure uninterrupted traffic flow.
Spec introduced the negotiation details about how to enable L0p from Configuration.Complete state along with FLIT mode with TS2 exchange. Once both sides support it, how to request down or up link size, how to ack or reject, and the detailed handshake mechanism are explained in Chapter 188.8.131.52. Moreover, the new mechanism uses a new Link Management DLLP to carry the expected value.
Below are the verification challenges for L0p mode:
In summary, PCIe 6.0 is a complex protocol with many verification challenges. You must understand many new Spec changes and think about the robust verification plan for the new features and backward compatible tests impacted by new features. Cadence’s PCIe 6.0 Verification IP is fully compliant with the latest PCIe Express 6.0 specifications and provides an effective and efficient way to verify the components interfacing with the PCIe 6.0 interface. Cadence VIP for PCIe 6.0 provides exhaustive verification of PCIe-based IP and SoCs, and we are working with Early Adopter customers to speed up every verification stage.