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The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer rate with PAM4 (Pulse Amplitude Modulation with 4 levels) modulation and uses FLIT (Flow Control Unit) as the unit of communication for efficiency. In What Disruptive Changes to Expect from PCI Express Gen 6.0? we covered what significant features PCIe 6.0 evolved to embrace.
Amongst many new features and changes in PCIe 6.0, we will talk about one major significant new feature: Training Sequences. The following mainly touches upon challenges and corresponding solutions based on our design and verification experiences. For more relevant PCIe 6.0 verification challenges, see Unraveling PCIe 6.0 FLIT Mode Challenges and Unraveling New Introduced PCIe 6.0 L0p.
Updates on Training Sequences in PCIe 6.0
TS1 and TS2 were used in every previous version but had their symbols positions redefined in 64GT/s. The symbol positions are entirely different from previous generations, and some symbols like link number and lane number maintain duplicate meanings, which is based on different LTSSM states.
In addition, an essential concept of valid halves was introduced for TS1/TS2 in 1b/1b. is the 16 bytes of each TS are composed of two halves of 8 bytes. For the receiving rules, if any half is valid, we consider the TS valid. Besides that, the scrambling rule for TS1/2 in 64GT/s speed slightly differs from other speeds.
When verifying TS1/TS2, we found several parts that might be interesting or challenging:
TS0 is the new TS used for Equalization in 64GT/s. It is used to communicate equalization information in specific symbols, which is just like TS1 does in previous versions. We need that because we consider that there may be many bit errors on the first entry to 64GT/s, so it has the same halves concept as TS1/TS2 in 64GT/s and even bits of all symbols are identical to odd bits for implementing NRZ encoding.
The first challenge here is that we must ensure that once we move to the Equalization state for 64GT/s, the model can transmit/receive the TS0 and decode it.
So, implement necessary checkers to check all new symbols and make sure halve concept is verified, which we have discussed in TS1/TS2.
The second challenge is that TS0 will be used in phase1/2 for Downstream Port and all phases for the upstream port.
There is a requirement that TS0 needs to be sent in the beginning of the phase2 for DP and the beginning of the phase3 for UP, then followed by TS1. We need to verify the TS0 behavior regarding phase transitions, timing requirement and the corner cases in Recovery.Equalization state.
The last one is that TS0 cannot be used in the non-Equalization state or phase3 of DP.
To make sure TS0 will not be sent or received at the wrong time and that DUT can handle the incorrect TS0 receiver, some EI test cases can be considered. Also, implementing a monitor to track all phase transitions and LTSSM state transitions and reporting errors if there is any protocol violation is highly recommended.
In summary, PCIe 6.0 is a complex protocol with many verification challenges. You must understand many new Spec changes and think about the robust verification plan for the new features and backward compatible tests impacted by new features. Cadence’s PCIe 6.0 Verification IP is fully compliant with the latest PCIe Express 6.0 specifications and provides an effective and efficient way to verify the components interfacing with the PCIe 6.0 interface. Cadence VIP for PCIe 6.0 provides exhaustive verification of PCIe-based IP and SoCs, and we are working with Early Adopter customers to speed up every verification stage.