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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification
Latest blogs

IBM and Cadence Collaboration Improves Verification Productivity

Technology leaders like IBM continuously seek opportunities to improve productivity…

• 2 min read
SystemVerilog , uvm , collaboration , IEEE 1800 , Metric Driven Verification , IBM , simvision , OVM , Tom Cole , Incisive , Mixed-Signal , Acellera VIP TSC , MDV , IEV , IES , vManager , IFV , IES-XL

Using the ‘restore -append_logs' Feature

As described in Specman Advanced Option appnote , Specman Elite supports dynamic…

• 3 min read
AF , Specman , debug , Functional Verification , restore append , reseeding , log files , e language , specman elite , restore , restore-append_logs , SAO , dynamic load , simulation

DVCon 2013 for Formal and ABV Users

At the upcoming DVCon (in San Jose, CA February 25-28) , Cadence will cover all aspects…

• 3 min read
Incisive Formal Verifier , Joe Hupcey III , ABV , Joerg Mueller , metric driven verification (MDV) , Functional Verification , Formal Analysis , NVIDIA , ABVIP , formal , formal apps , Vigyan Singhal , Incisive , Incisive Enterprise Verifier , Mike Stellfox , Chris Komar , Oski Technology , DVcon , assertions , formal scoreboard , MDV , IEV , Oski , Formal verification , IFV , Assertion-based verification

DVCon 2013 for the Specmaniac

At the upcoming DVCon (in San Jose, CA February 25-28) , Cadence will cover all aspects…

• 3 min read
Specman , Specman/e , methodology , verification strategy , metric driven verification (MDV) , debug , Functional Verification , Formal Analysis , formal , Incisive Debug Analyzer , e , e language , Mike Stellfox , DVcon , Aspect Oriented Programming , simulation , AOP , verification

Improve Debug Productivity - SimVision Video Series on YouTube

Most verification customers claim that they are spending over 50% of their verification…

• less than a min read
SystemVerilog , Low Power , : Functional Verification , transaction , watch window , metric driven verification (MDV) , cadence , debug , Functional Verification , Debug Performance , UVM-MS , RTL , simvision , Incisive Enterprise Simulator , SimVision watch window , EDA360 , Coverage-Driven Verification , Mixed Signal Verification , Incisive , Verilog , bug , sequences , RTL design , video tutorial , IEV , Incisive Enterprise Simulator (IES) , VHDL , debugging , IES , IFV , IES-XL

A Concrete Linux Virtual Platform Example

Virtual platforms are used to find many different types of system and software issues…

• 3 min read
Device Drivers , zynq , virtual platforms , virtual prototypes , UART , embedded software , Ubuntu , softtware bugs , SystemC , xilinx , Zynq virtual platform , debugging software , linux , Jason Andrews , Zynq-7000 , System Design and Verification

A 10-year Look-Back from 2013 – Some Technology Predictions that are Coming True…

It is January 2013, the year has begun and it is time for my annual 10 year look…

• 4 min read
SystemVerilog , Apple , Low Power , integration , Google Glass , virtual platforms , tungsten , GPS , Cell Phone , base stations , MP3 , virtual prototypes , IBM , Harry Goldstein , PDA , abstraction , google , Linda Geppert , 10 year , Palm , hardware/software CoDesign , 10 year look-back , software , IEEE Spectrum , Mark. E. Dean , Schirrmeister , ESL , iPhone , ESL system-level design

Specman: An Assumed Generation Issue and its Real Root Cause

Random generation is always a complex task, and differences in results are usually…

• 2 min read
AF , IntelliGen , Specman , debug , Functional Verification , garbage collection , lists , Incisive , e code , Generation , e language , assumed generation , Funcional Verification , Zander , vManager , random generation

2013 CES: Top 4 Trends Benefiting EDA

While a variety of EDA customer segments are growing, consumer electronics continues…

• 5 min read
Automotive , mobile devices , Verification IP , Design IP , Joe Hupcey III , IP , Consumer Electronics Show , CES , 14nm , SoC , apps , UltraHD TVs , verification

Specman: Determining a Good Value for optimal_process_size

Specman's Automatic GC Settings mechanism is aimed at eliminating the need for users…

• 7 min read
AF , memory usage , optimal_process_size , Specman , garbage collection , Functional Verification' signal integrity , e language , optimal process size , memory consumption , OPS

System Design 2012 – Real Users Achieving Real Results!

This morning the final success story my team has been working on for this year went…

• 4 min read
ESL Market , Nufront , Altair , FPGA Based Prototyping , Verification Computing Platform , Virtual System Platform , cadence , Sigma , Acceleration , Functional Verification , LeCroy , Dynamic Power Analysis , Doulog , System Design and Verification , Freescale , Methods2Business , System Development Suite , Samsung , embedded software , Rohde & Schwarz , Ericsson , LSI , Palladium XP , Emulation , CSR , CDNLive! , ST Microelectronics , Texas Instruments , xilinx , DAC 2012 , ARM , Schirrmeister , Accelerated Verification IP , low power optimization

University of Aizu and Cadence Collaborate to Deliver a Course Featuring High-Level…

Today we issued a Japan-only press release announcing a high-level synthesis joint…

• 2 min read
High-Level Synthesis , university , TLM-driven design , TLM , japan , SystemC , C-to-Silicon Compiler , DAC 2012 , Aizu , C++

C-to-Silicon 12.2 Available for Your Holiday Shopping List

The winter holiday season is that special time of year when we get bombarded with…

• 4 min read
High-Level Synthesis , Flex Channels , C-to-Silicon 12.2 , Jack Erickson , IP re-use , rtl compiler , SystemC , C-to-Silicon Compiler , HLS , clock gating , QoR , System Design and Verification

Securing the Internet of Things

While I had looked at the challenges of hardware/software integration in various…

• 3 min read
security , Intel , device security , hackers , System Development Suite , Amphion Forum , embedded software , Green Hills , burning printer , Mocana , software security , cyber attacks , Internet of Things , phone emissions , Schirrmeister , HW/SW Co-Development

Avoid Overly Long Expressions in Specman e Code

When you write your e code, a good practice is to avoid expressions that are "overly…

• 3 min read
AF , parsing , Specman , Functional Verification , long expressions , e code , e language

Update to the Linux Kernel Message System

A few months ago I wrote an Introduction to the Linux Kernel Message System . As…

• 1 min read
Virtual System Platform , virtual platforms , GDB , VAP , cadence , ring buffer , uncompressing Linux , virtual prototypes , System Design and Verification , kernel message system , booting Linux , embedded software , VSP , Imperas , software development , Zynq virtual platform , linux , Zynq-7000 , Embedded Linux , ESL , kernel messaging system , Andrews

Speed Verification Turnaround by Extending Metric-Driven Verification (MDV) to T…

One of the main benefits of moving the design entry point up in abstraction from…

• 1 min read
uvm , TLM , Jack Erickson , Functional Verification , abstraction , webinar , metric-driven verification , SystemC , Watanabe , MDV , System Design and Verification

New Product: ARM ACE Assertion-Based Verification IP (ABVIP) Available Now

Preface: on Tuesday December 11 we are giving a free a webinar on "ACE Assertion…

• 1 min read
ACE , ABV , Joerg Mueller , ABVIP , Mirit Fromovich , ACE verification , ARM , AMBA4

Techniques to Boost Incisive Simulation Performance

Functional verification is the biggest challenge in delivering more complex electronic…

• 3 min read
performance , Accleration , simulation speed , Incisive Enterprise Simulator (IES)

UVM e vr_ad -- Specman Read/Write Register Enhancements

If you are a Specman vr_ad user, you probably know that register access is implemented…

• 1 min read
AF , uvm , Specman , Functional Verification , vr_ad , Register Package , e language , UVMe , register enhancements

Optimizing ARM Based Designs for Low Power using Emulation

The month November goes to the Brits, no question. Not only did the James Bond movie…

• 5 min read
ESL Market , Nufront , FPGA Based Prototyping , Verification Computing Platform , Virtual System Platform , Peng Wang , cadence , Acceleration , Functional Verification , Dynamic Power Analysis , System Design and Verification , System Development Suite , embedded software , Palladium XP , Emulation , ARM , Schirrmeister , low power optimization

Need e/Specman Expertise ASAP? Free Training and Verification Alliance Partners Are…

Recently an EDA industry observer relayed some Specmaniacs' concerns about satisfying…

• less than a min read
IEEE 1647 , Specman , Hannes Froehlich , Functional Verification , MOOC , Udacity , training , VA Partners , verification alliance , e language

CDNLive paper: High-level Synthesis on Video Processing ASIC

The proceedings from the recent CDNLive! event in Israel recently became available…

• 1 min read
High-Level Synthesis , video processor , Jack Erickson , CDNLive , System Design and Verification , Freescale , rtl compiler , C-to-Silicon , Israel , SystemC , CDNLive! , DAC 2012 , HLS , ESL

Function Level C Interface – New C Interface for Specman

Working with the conventional Specman C language interface has two major disadvantages…

• 2 min read
AF , Specman , function level , Functional Verification , C Interface , e language , Specman C , TCM , PLI

Creating Custom File Systems and the Linux Loop Device

A few weeks ago we had a crisis at our house. My son managed to delete the data from…

• 7 min read
virtual platforms , Linux loop , File System , virtual prototypes , chroot , System Design and Verification , embedded software , Ubuntu , linaro , custom file systems , mount -o loop , ARM Architecture , Zynq virtual platform , linux , Jason Andrews , Zynq-7000 , simulation

How Many Cycles are Needed to Verify ARM’s big.LITTLE on Palladium XP?

At the recent CDNLive! India user conference, Deepak Venkatesan and Murtaza Johar…

• 5 min read
ESL Market , FPGA Based Prototyping , Verification Computing Platform , Virtual System Platform , cadence , Acceleration , Functional Verification , System Design and Verification , big.LITTLE , System Development Suite , embedded software , Palladium XP , Emulation , ARM , cost of ownership

Event Report: Club Formal San Jose – Features and Techniques for Experts, Verification…

Last week over 35 power users from over a dozen companies came together for the latest…

• 5 min read
Incisive Formal Verifier , ABV , Team Verify , Functional Verification , Formal Analysis , formal apps , Vigyan Singhal , Incisive , Incisive Enterprise Verifier , Chelsio , Chris Komar , apps , assertions , Club Formal , bypass logic verification , IEV , Oski , Formal verification , IFV , liveness , Assertion-based verification

Ubuntu 12.10 on a Virtual Platform at ARM Techcon

Next week (Oct. 30-Nov. 1) ARM TechCon 2012 is at the Santa Clara Convention Center…

• 1 min read
ARM Techcon , Virtual System Platform , virtual platforms , programmer's guide , virtual prototypes , Cortex-A9 , Cortex-A , VSP , Ubuntu , ARM , Quantal Quetzal , Ubuntu 12.10 , linux , Jason Andrews , Zynq-7000
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