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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification
Latest blogs

Some Final Real-World Assertions for the Holidays

My last "real-world assertions" blog post seems to have tickled a bunch of people…

• 3 min read
holidays , ABV , Functional Verification , assertions , real-world assertions , Assertion-based verification

Video: Incisive Formal Verifier R&D Leader Pradeep Goyal talks about Expert Formal…

Continuing the series that introduces you to the people that create the tools you…

• less than a min read
Pradeep Goyal , Joe Hupcey III , ABV , Functional Verification , Formal Analysis , Model-checking , formal , Incisive , assertions , Formal verification , IFV , verification , Assertion-based verification

High Level Synthesis for a Control-Dominated Design?

CDNLive! conferences are full of interesting and helpful presentations by customers…

• 1 min read
High-Level Synthesis , control-dominated , CDNLive , C to Silicon , Freescale , control , SystemC , CDNLive! , HLS , FPGA , System Design and Verification

Equine Anatomy, Pax Romana and the Reach of Standards

At the recent Synopsys EDA Interoperability Forum, the opening session focused on…

• 5 min read
pax romana , IP , markets , virtual platforms , TLM , horses , Acceleration , Standards , OSCI , Hogan , embedded software , Magarshack , Goodenough , system design , system , Accellera , Jim Hogan , SoC Realization , SystemC , interoperability , high level synthesis , ESL , architect , System Design and Verification

Early Holiday Present: Sudoku Solver Using Incisive Enterprise Verifier (IEV) and…

Allow me to interrupt the excellent "Meet R&D" series to share a small holiday present…

• 1 min read
ABV , Joerg Mueller , formal , simvision , Sudoku , ADS , PSL , IEV , Assertion-Driven Simulation , Formal verification

Report on ARM Techcon 2011: Real and Virtual Software Apps, High-Speed Silicon and…

The acid test of any conference is how long the information and lessons learned linger…

• 4 min read
ARM Techcon , Charbax , Joe Hupcey III , Virtual System Platform , Richard Goering , 20nm , 14nm , EDA360 , VSP , YouTube , Lego , robot , Chi-Ping Hsu , ARM , Steve Leibson , Jason Andrews , Rubik's Cube

Embracing Our Competitors with the Connections Program

In my last blog post , I described the Cadence Verification Alliance (VA) and how…

• 2 min read
NextOp , collaboration , Zocalo , Functional Verification , partnerships , VA , VIP , EDA360 , Duolog , verification alliance , Connections , interoperability , verification

Holiday Idea #1: Give the Gift of UVM Knowledge

Your favorite verification engineer has been good all year. Thousands of tests run…

• 2 min read
uvm , OVM , Incisive Enterprise Simulator , Accellera VIP TSC , UVM training , IES , IES-XL

Secrets of the (Verification) Alliance

In a recent post , I discussed the need for cross-vendor cooperation in EDA, especially…

• 3 min read
uvm , collaboration , Specman , Functional Verification , VAalliance , partnerships , VA , VIP , EDA360 , EDA , Verisity , verification alliance , Doulos , AMIQ , Oski , verification

Video: Meet Incisive Enterprise Verifier R&D Architect Vinaya Singh

Continuing the series of introducing you to the people that create the tools you…

• less than a min read
Joe Hupcey III , ABV , Vinaya Singh , Functional Verification , Formal Analysis , formal , video , assertions , IEV , Assertion-Driven Simulation , Formal verification , Assertion-based verification

Update to the OVM Register Package

OVM users have something new to give thanks for this holiday season -- an update…

• 2 min read
uvm , IP-XACT , Functional Verification , OVM , Register Package , Incisive , IES , OVMWorld , verification

Video: Meet Formal and ABV R&D Team Leader Deepak Pant

Inspired by the positive response to my interview of Formal R&D Distinguished Engineer…

• less than a min read
Alok Jain , ABV , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , Deepak Pant , video , ADS , assertions , IEV , Formal verification , IFV , Assertion-based verification

How Will High-Level Synthesis Affect the Make vs. Buy vs. Re-use Decision?

During the planning phase for SoC designs, teams have to choose whether to "make…

• 2 min read
High-Level Synthesis , IP , TLM , System Design and Verification , C-to-Silcon , IP re-use , re-use , reuse , SystemC , C-to-Silicon Compiler

Will Software Development Cause Another “Industrial” Revolution?

As you have read here before, Cadence has been working closely with Xilinx to create…

• 3 min read
zynq , edaForum , virtual prototypes , industrial , System-Level Design , Siemens , Virtual Platforms , Industrial Automation , Design Flows , Sanitas

India Needs Real-World Assertions Too

I've just returned from a week-long trip to India, spending most of my time at the…

• 4 min read
Functional Verification , Old Delhi , Noida , assertions , New Delhi , real-world assertions , India

Parallel Compilation for SystemC

One of the most common complaints about SystemC is that it takes too long to compile…

• 3 min read
Virtual System Platform , virtual platforms , GNU , parallel compilation , virtual prototypes , embedded software , C , LSF , compile , pallallel compile , make , SystemC , System Design and Verification

Event Report: Club Formal Shanghai

The first "Club Formal" event in China was held in Shanghai on Oct. 21 2011, and…

• 2 min read
events , Verification IP , China , ABV , verification strategy , Functional Verification , ABVIP , formal , ADS , assertions , Club Formal , IEV , Assertion-Driven Simulation , Shanghai , Formal verification , IFV , Jin Tang , Assertion-based verification

Report on CDNLive! India 2011: Provocative Keynotes, Detailed Papers, and Robots…

Recently I had the honor of presenting the functional verification roadmap at CDNLive…

• 2 min read
Suman Ray , Low Power , Joe Hupcey III , ABV , Apurva Kalia , verification strategy , CDNLive , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , Manu Chopra , Incisive , Lokesh Pundreeka , SVA , Lego , assertions , robot , MDV , Rubik's Cube , Formal verification , IFV , Assertion-based verification

Shameless Promotion: Free Club Formal San Jose, Formal Scoreboard Webinar

Please join Team Verify and other D&V engineers for one or both of the following…

• 1 min read
scoreboard , ABV , methodology , verification strategy , Joerg Mueller , Functional Verification , Formal Analysis , formal , EDA360 , webinar , Club Formal , IEV , Formal verification , IFV , Assertion-based verification

Welcome to the Zynq-7000 Virtual Platform

As you might guess we are pretty excited about the Virtual Platform development for…

• 4 min read
zynq , virtual platforms , TLM , EPP , Zynq-7000' , virtual prototypes , Cortex-A9 , System Design and Verification , software , SystemC , xilinx , ARM , linux , extensible , FPGA

Verification and the Need for Collaboration

Earlier this week I was at the ARM TechCon in Santa Clara, a show that gets better…

• 2 min read
NextOp , ARM Techcon , uvm , collaboration , Zocalo , Functional Verification , Standards , partnerships , VA , EDA360 , EDA , Duolog , verification alliance , UCIS , AMIQ

Report: Formal Analysis Papers at CDNLive India 2011

On October 19, 2011 in Bangalore, India more than 800 engineers across all domains…

• 3 min read
ABV , CDNLive , Functional Verification , Formal Analysis , ABVIP , formal , Lokesh Pundreeka , ADS , metric-driven verification , assertions , MDV , IEV , Assertion-Driven Simulation , Formal verification , IFV , India , Assertion-based verification

Virtual Platform UART Use Number 4: Connecting to an RTOS Tracing Framework

This is the last installment of my series on different uses for the UART in Virtual…

• 4 min read
Virtual System Platform , virtual platforms , Quantum Platform , virtual prototypes , dining philosophers , UART , System Design and Verification , RTOS tracing , QP , software , qspy

Come See How to Connect SystemVerilog and SystemC Using UVM

All pun-tastic references aside, connecting SystemVerilog and SystemC is becoming…

• 1 min read
SystemVerilog , uvm , OVM ML , Functional Verification , webinar , multi-language , SystemC , IES

Too Many Missing Real-World Assertions?

Well, here I am embarking on my fifth post in which I point out illogical situations…

• 4 min read
ABV , Functional Verification , formal , assertions , Assertion-based verification

Formal Verification with Asynchronous Clocks

Many designs have multiple independent clock inputs with different frequency specifications…

• 2 min read
ABV , asssertion-based verification , Joerg Mueller , Verification methodology , Functional Verification , Formal Analysis , formal , SVA , PSL , assertions , IEV , Formal verification , IFV , verification

Automating UVM to Tackle Insidious HW/SW Bugs

You've just sat through a 2-hour program review. The 30 minutes you spent describing…

• 1 min read
SystemVerilog , uvm , bugs , Duolog , universal verification methodology , Accellera VIP TSC , David Murray , IES

Free Webinar Thursday 10/13 -- Automating Assertion Generation for Simulation, Formal…

Everyone can agree that Assertion-Based Verification (ABV) is a powerful methodology…

• 1 min read
NextOp , Joe Hupcey III , ABV , methodology , interview , Formal Analysis , BugScope , Incisive , webinar , DVcon , assertion synthesis , assertions , IEV , Yuan Lu , Formal verification , IFV , Assertion-based verification , IES-XL
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