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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification

Latest blogs

CCIX Coherency: Verification Challenges and Approaches

Cache coherency is not a new concept. Coherent architectures have existed for many…

• 2 min read
Verification IP , ccix , SoC , coherency , System Verification

Cadence Collaborates with Test & Verification Solutions on Portable Stimulus

The Cadence® Connections® Verification Program brings together a worldwide network…

• 2 min read
CDNLive , Test , DVcon , pss , verification

This Was 2017, Looking Forward 2018

With 2017 just out of the door, this is a good time to stop for a few minutes, look…

• less than a min read
Specman , Functional Verification

CRAFTing Your Aero/Defense UVM Testbench the Easy Way

So you want to build an automated testbench for your aero/defense project, eh? Luckily…

• 2 min read
Functional Verification , VWB , online tool , automated testbench , craft

User Extensions to DUT Error

A question was raised to stackoverflow about how can one extend the dut _error()…

• 2 min read
Specman , e code , advanced verification , e language

App Note Spotlight - Introduction to Connect Modules

Welcome to the App Note Spotlight—a bi-weekly series where the XTeam highlights an…

• 3 min read
app note , Functional Verification , App Note Spotlight , Connect Module , mixed signal

Portable Stimulus User Gives Perspec PSS Technology Nearly Perfect Review

It’s always good to hear what real users think of products. Here is a very detailed…

• 3 min read

Register for the UVM Register Layer Webinar on January 12!

On Friday, January 12, Doulos is hosting a UVM Register Layer webinar, with the aim…

• less than a min read
webinar , Doulos , xcelium , uvm register layer

Perspec System Verifier is #1 in Portable Stimulus in 2017 User Survey

It’s now official: Perspec System Verifier is rated the #1 product in the #1 category…

• 3 min read

Check Again: Cadence Announces Release of the First PCIe 5.0 VIP—With TripleCheck…

On November 28, 2017, Cadence announced the release of the first available PCIe®…

• 1 min read
Functional Verification , PCI-e , announcement , TripleCheck

26262 4U: Infineon and the Incisive Functional Safety Simulator

Infineon and Cadence have a bit of a history: they’ve been working together on functional…

• 2 min read
Infineon , Functional Verification , fault , ifss

Slaying the Gate-Level Simulation (GLS) Dragon: Your Knight Is Here!

Even today, gate-level simulation is still a major signoff step for most semiconductor…

• 2 min read
app note , Functional Verification , GLS

Adding Annotations in Your e Code

If you have had a chance to work with languages like Java or C#, you might have come…

• 6 min read
Specman , e , e language , specman elite , annotations

Cadence and Arm Announce Early Access to Xcelium Parallel Logic Simulators on Arm…

On October 24, Cadence and Arm announced early access to the Xcelium Parallel Logic…

• 1 min read
Multi-Core , xcelium , ARM , simulation , announcement

Munich October 18—Come See SystemC Evolution Day!

Sorry, you missed Oktoberfest (which is mostly in September anyway). But come to…

• 2 min read
Munich , Functional Verification , Accellera , SystemC , event

Mediatek Deploys Perspec for SoC Verification of Low Power Management (part 3 of…

Here we conclude the blog series and highlight the results of Mediatek 's use of…

• 1 min read
uvm , Perspec , coherent , perspec system verifier , coherency library , coherency , Accellera , mediatek , ARM , pss , portable stimulus

Teradyne Standardizes on Xcelium Simulator

Today, Cadence announced that Teradyne has adopted the Xcelium™ Parallel Simulator…

• less than a min read
Teradyne , ASIC , press release , xcelium , JasperGold , vManager

Teradyne "Formally" Adopts JasperGold FPV

CDNLive Boston 2017: Teradyne reveals their success with JasperGold in their presentation…

• 2 min read
Teradyne , FPV , CDNLive , customer success , JasperGold , Formal verification

Celebrating Five Years of Performance-Optimized Arm-Based SoCs: Now including AM…

It’s been quite a long 5-year journey building and deploying Performance Analysis…

• 2 min read
iwb , interconnect , amba5 , Interconnect Workbench , Palladium , Performance Analysis , AMBA , CoreLink , xcelium , ARM

When Arm meets Intel – Overcoming the Challenges of Merging Architectures on an SoC…

As the stakes for winning server segment market share grow ever higher an increasing…

• 2 min read
SoC verification , perspec system verifier , Accellera , pss , portable stimulus

Single Core vs. Multi Core: Simulation in Stereo

Latency simulations are the sworn enemy of the verification schedule. A handful of…

• 2 min read
Single-Core , Functional Verification , Multi-Core , xcelium , simulation

Making it Easier to Apply Palladium Z1 to SoC Performance Analysis

Recently, Renesas combined the Cadence® Interconnect Workbench, the Cadence vManager…

• 1 min read
Interconnect Workbench , customer feedback , success story , Palladium , Renesas

How to Get to a Trillion Devices in the Internet of Things in 2035

Next month at Arm TechCon, one of the key discussion topics with be the internet…

• 4 min read
prototyping , cadence , palladium z1 , IoT , Socrates , Emulation , Internet of Things , ARM , protium s1 , verification

How To Create L3 Cache Command Overflow Stress Test in Less Than 2 Days

One category of difficult SoC tests to create are stress tests, to validate the limits…

• 4 min read
SoC verification , perspec system verifier , Accellera , pss , portable stimulus

Put On Your Perspectacles: How Perspec Can Speed Up Your Testbench

It’s no secret that the bulk of time running simulations is spent on the testbench…

• 3 min read
Functional Verification , Perspec , xcelium , testbench

Do You Have The Tools You Need To Verify Your ARM Multi-core, Coherent SoC?

Multi-core, coherent SoCs are very complex and verifying their behavior requires…

• 1 min read
SoC verification , perspec system verifier , Accellera , ARM , pss , portable stimulus

Save & Restore with More: Preserve Your Entire SoC

The concept of Save and Restore is simple: instead of re-initializing your simulation…

• 3 min read
Functional Verification , x-team , update , xcelium simulator , feature , productivity , xcelium , save and restore

Infineon’s Coverage-Driven Distribution: Shortcutting the MDV Loop

There are more ways to improve productivity in the verification process than simply…

• 3 min read
Specman , CDD , CDNLive , Infineon , Functional Verification , e language , efficiency , MDV
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