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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification

Latest blogs

Develop for Debugability – Part 1

Debugging is the most time-critical activity of any verification engineer. Finding…

• 4 min read
AF , Specman , debug , Functional Verification , encapsulate , aspect-oriented programming , encapsulating aspects , debugability , e language , Incisive Enterprise Simulator (IES) , debugging , simulation , verification , Daniel Bayer

Incisive Debug Analyzer is a Finalist for EETimes and EDN ACE Software Product of…

Great news.... Incisive Debug Analyzer (IDA) is one of five finalists for the EETimes…

• 2 min read
SystemVerilog , IDA: Functional Verification , ACE , Specman , Specman/e , cadence , debug , Specman e , Incisive Enterprise Simulator , Incisive Debug Analyzer , EDA , Incisive , e , Incisive Enterprise Simulator (IES) , simulation , IUS , EE Times

What to See at the DATE Conference: High-Level Synthesis

The DATE (Design Automation and Test in Europe) Conference is next week (March 18…

• 1 min read
High-Level Synthesis , DATE , Alex Kondratyev , C-to-Silicon Compiler , HLS , system-level , ESL , QoR , System Design and Verification

Specman: Getting Source Information on Macros

When you write a define-as or define-as-computed e macro, you sometimes need the…

• 2 min read
AF , Specman , Functional Verification , source information on macros , e language , team specman , macros , messages

DVCon 2013: Functional Verification Is EDA’s “Killer App”

With another year of record attendance, DVCon has again proven that a functional…

• 3 min read
Joe Hupcey III , Specman , methodology , Team Verify , DVCon 2013 , metric driven verification (MDV) , Functional Verification , Formal Analysis , UVM e , Specman e , formal , formal apps , Richard Goering , e code , e , e language , DVcon , apps , papers , metrics , verification

System to Silicon Verification – CDNLive Gives a Reality Check on How Hardware and…

Ever since switching from being a hardware/software chip developer to being an enabler…

• 4 min read
AVIP , Intel , Verification IP , RPP , Low Power , Verification Computing Platform , Virtual System Platform , Fast Models , PXP , CDNLive , cadence , Acceleration , Teledyne LeCroy FPGA Based Prototyping , System to Silicon Verification , AMD , Dynamic Power Analysis , System Design and Verification , System Development Suite , Samsung , embedded software , VSP , Incisive , Palladium XP , Emulation , Imperas , Freescael , Bluespec , CDNLive! , ARM , Schirrmeister , Accelerated Verification IP , low power optimization , VCP

Securing Invisible Things … or “Why Denial Works!”

The opening keynote of the Embedded World conference in Germany left me with chills…

• 4 min read
security , Automotive , FPGA Based Prototyping , Verification Computing Platform , Virtual System Platform , Vulnerabilities , cadence , Acceleration , Functional Verification , Safety , McClure , System Design and Verification , System Development Suite , Driver Assist , embedded software , Palladium XP , Emulation , DVcon , Testing , Cylance , ADAS , ARM , Error Injection , Embedded World , Schirrmeister , Hacking Exposed , verification

Application Specific System-Design and Verification at Embedded World and DVCon

This week (February 25th 2013) is a busy one for system development and the Cadence…

• 3 min read
Nuremberg , virtual platforms , applications , virtual prototypes , System Design and Verification , application-specific , Mobile World Congress , System Development Suite , embedded software , automotive electronics , Internet of Things , software , DVcon , apps , software development , hardware/software , embedded systems , Embedded World , Schirrmeister

Embedded World 2013: Virtual Platforms Connected to Everything

Sometimes it is hard to explain why certain ideas take off and why others don’t.…

• 3 min read
virtual prototyping , RPP , Virtual System Platform , virtual platforms , embedded world conference , embedded software , VSP , Palladium XP , Emulation , system design , Rapid Prototyping Platform , System Design & Verification , Embedded World , linux , simulation

What the 787 Dreamliner Can Teach Us About SoC design

The commercial aircraft industry is at a stage where it innovates at a much slower…

• 6 min read
Dreamliner , Boeing , Apple , 787 Dreamliner , TLM , fire , 787 , C-to-Silcon , Harvard Business Review , SoC , IP assembly , system design , SoC design , Apple A6 , SystemC , outsourcing , iPhone , Jay-Z , System Design and Verification

Planning to Go to DVCon 2013 Next Week? If So, Don't Miss the Debug Tutorial Feb…

TUTORIAL : Fast Track Your UVM Debug Productivity with Simulation and Acceleration…

• 1 min read
SystemVerilog , Specman/e , AVS , metric driven verification (MDV) , debug , Functional Verification , Debug Performance , debug tutorial , Incisive Debug Analyzer , Mixed Signal Verification , DVcon , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , IES , IES-XL

Why C-to-Silicon Compiler HLS has Supported IEEE 1666-2011 SystemC All Along

Recently one of our competitors issued a press release claiming to be the first high…

• 1 min read
asynchronous reset , IEEE 1666-2011 , Incisive , SystemC , C-to-Silicon Compiler , QoR

IBM and Cadence Collaboration Improves Verification Productivity

Technology leaders like IBM continuously seek opportunities to improve productivity…

• 2 min read
SystemVerilog , uvm , collaboration , IEEE 1800 , Metric Driven Verification , IBM , simvision , OVM , Tom Cole , Incisive , Mixed-Signal , Acellera VIP TSC , MDV , IEV , IES , vManager , IFV , IES-XL

Using the ‘restore -append_logs' Feature

As described in Specman Advanced Option appnote , Specman Elite supports dynamic…

• 3 min read
AF , Specman , debug , Functional Verification , restore append , reseeding , log files , e language , specman elite , restore , restore-append_logs , SAO , dynamic load , simulation

DVCon 2013 for Formal and ABV Users

At the upcoming DVCon (in San Jose, CA February 25-28) , Cadence will cover all aspects…

• 3 min read
Incisive Formal Verifier , Joe Hupcey III , ABV , Joerg Mueller , metric driven verification (MDV) , Functional Verification , Formal Analysis , NVIDIA , ABVIP , formal , formal apps , Vigyan Singhal , Incisive , Incisive Enterprise Verifier , Mike Stellfox , Chris Komar , Oski Technology , DVcon , assertions , formal scoreboard , MDV , IEV , Oski , Formal verification , IFV , Assertion-based verification

DVCon 2013 for the Specmaniac

At the upcoming DVCon (in San Jose, CA February 25-28) , Cadence will cover all aspects…

• 3 min read
Specman , Specman/e , methodology , verification strategy , metric driven verification (MDV) , debug , Functional Verification , Formal Analysis , formal , Incisive Debug Analyzer , e , e language , Mike Stellfox , DVcon , Aspect Oriented Programming , simulation , AOP , verification

Improve Debug Productivity - SimVision Video Series on YouTube

Most verification customers claim that they are spending over 50% of their verification…

• less than a min read
SystemVerilog , Low Power , : Functional Verification , transaction , watch window , metric driven verification (MDV) , cadence , debug , Functional Verification , Debug Performance , UVM-MS , RTL , simvision , Incisive Enterprise Simulator , SimVision watch window , EDA360 , Coverage-Driven Verification , Mixed Signal Verification , Incisive , Verilog , bug , sequences , RTL design , video tutorial , IEV , Incisive Enterprise Simulator (IES) , VHDL , debugging , IES , IFV , IES-XL

A Concrete Linux Virtual Platform Example

Virtual platforms are used to find many different types of system and software issues…

• 3 min read
Device Drivers , zynq , virtual platforms , virtual prototypes , UART , embedded software , Ubuntu , softtware bugs , SystemC , xilinx , Zynq virtual platform , debugging software , linux , Jason Andrews , Zynq-7000 , System Design and Verification

A 10-year Look-Back from 2013 – Some Technology Predictions that are Coming True…

It is January 2013, the year has begun and it is time for my annual 10 year look…

• 4 min read
SystemVerilog , Apple , Low Power , integration , Google Glass , virtual platforms , tungsten , GPS , Cell Phone , base stations , MP3 , virtual prototypes , IBM , Harry Goldstein , PDA , abstraction , google , Linda Geppert , 10 year , Palm , hardware/software CoDesign , 10 year look-back , software , IEEE Spectrum , Mark. E. Dean , Schirrmeister , ESL , iPhone , ESL system-level design

Specman: An Assumed Generation Issue and its Real Root Cause

Random generation is always a complex task, and differences in results are usually…

• 2 min read
AF , IntelliGen , Specman , debug , Functional Verification , garbage collection , lists , Incisive , e code , Generation , e language , assumed generation , Funcional Verification , Zander , vManager , random generation

2013 CES: Top 4 Trends Benefiting EDA

While a variety of EDA customer segments are growing, consumer electronics continues…

• 5 min read
Automotive , mobile devices , Verification IP , Design IP , Joe Hupcey III , IP , Consumer Electronics Show , CES , 14nm , SoC , apps , UltraHD TVs , verification

Specman: Determining a Good Value for optimal_process_size

Specman's Automatic GC Settings mechanism is aimed at eliminating the need for users…

• 7 min read
AF , memory usage , optimal_process_size , Specman , garbage collection , Functional Verification' signal integrity , e language , optimal process size , memory consumption , OPS

System Design 2012 – Real Users Achieving Real Results!

This morning the final success story my team has been working on for this year went…

• 4 min read
ESL Market , Nufront , Altair , FPGA Based Prototyping , Verification Computing Platform , Virtual System Platform , cadence , Sigma , Acceleration , Functional Verification , LeCroy , Dynamic Power Analysis , Doulog , System Design and Verification , Freescale , Methods2Business , System Development Suite , Samsung , embedded software , Rohde & Schwarz , Ericsson , LSI , Palladium XP , Emulation , CSR , CDNLive! , ST Microelectronics , Texas Instruments , xilinx , DAC 2012 , ARM , Schirrmeister , Accelerated Verification IP , low power optimization

University of Aizu and Cadence Collaborate to Deliver a Course Featuring High-Level…

Today we issued a Japan-only press release announcing a high-level synthesis joint…

• 2 min read
High-Level Synthesis , university , TLM-driven design , TLM , japan , SystemC , C-to-Silicon Compiler , DAC 2012 , Aizu , C++

C-to-Silicon 12.2 Available for Your Holiday Shopping List

The winter holiday season is that special time of year when we get bombarded with…

• 4 min read
High-Level Synthesis , Flex Channels , C-to-Silicon 12.2 , Jack Erickson , IP re-use , rtl compiler , SystemC , C-to-Silicon Compiler , HLS , clock gating , QoR , System Design and Verification

Securing the Internet of Things

While I had looked at the challenges of hardware/software integration in various…

• 3 min read
security , Intel , device security , hackers , System Development Suite , Amphion Forum , embedded software , Green Hills , burning printer , Mocana , software security , cyber attacks , Internet of Things , phone emissions , Schirrmeister , HW/SW Co-Development

Avoid Overly Long Expressions in Specman e Code

When you write your e code, a good practice is to avoid expressions that are "overly…

• 3 min read
AF , parsing , Specman , Functional Verification , long expressions , e code , e language

Update to the Linux Kernel Message System

A few months ago I wrote an Introduction to the Linux Kernel Message System . As…

• 1 min read
Virtual System Platform , virtual platforms , GDB , VAP , cadence , ring buffer , uncompressing Linux , virtual prototypes , System Design and Verification , kernel message system , booting Linux , embedded software , VSP , Imperas , software development , Zynq virtual platform , linux , Zynq-7000 , Embedded Linux , ESL , kernel messaging system , Andrews
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