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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification
Latest blogs

DAC 2012: Enabling the Programming of an Extensible Processing Platform

We at Cadence have been writing about the virtual prototype associated with the Xilinx…

• 6 min read
DAC , Virtual System Platform , cadence , debug , Functional Verification , System Design and Verification , System Development Suite , embedded software , virtual prototype , Software Development and Debug , firmware , Performance Analysis , xilinx , DAC 2012 , Design Automation Conference , system integration

High-Level Design and Verification: How Can We Finally Move on From the Forrest Gump…

Richard Goering wrote an excellent summary of the DAC panel "High Level Synthesis…

• 3 min read
DAC , TLM , DAC panel , high-level verification , RTL , Forrest Gump , high-level design , SoC , System Design & Verification , SystemC , C-to-Silicon Compiler , high level synthesis , HLS , C++ , ESL , verification

Video: DAC 2012 Discussion with EET's Brian Fuller on EDA and Video

Continuing our conversation on leveraging social media for EDA, at the Design Automation…

• 1 min read
Brian Fuller , Joe Hupcey III , interview , video , Blogging , Social Media , DAC 2012 , EE Times

Video: Oski Technology’s Courageous "72 hour Verification Challenge" Using Incisive…

I've seen a lot of intriguing promotions over the years, but at DAC 2012 our partners…

• 1 min read
DAC , Joe Hupcey III , ABV , Functional Verification , bugs , NVIDIA , formal , Vigyan Singhal , Oski Technology , assertions , DAC 2012 , IEV , Formal verification , IFV , verification , Assertion-based verification

DAC 2012 Best User Track Paper Review: Deploying Model Checking for Bypass Verif…

Bypass logic verification is a common and difficult challenge for modern VLSI design…

• 3 min read
DAC , ABV , DAC best paper , Functional Verification , formal , Vigyan Singhal , bypass verification , bypass logic , User Track , papers , DAC 2012 , IEV , Darrow Chu , Formal verification

Photo Essay and Comments on DAC 2012 in San Francisco, CA

In addition to the annotated image gallery (click here or on the image), below are…

• 3 min read
gallery , DAC , Joe Hupcey III , ABV , CDNLive , Functional Verification , formal , "Coverage Unreachability" , formal apps , Richard Goering , 20nm , Vigyan Singhal , bypass verification , Denali Party , UCIS , DVcon , Accellera , Lego , Hosted Design Solutions , DAC 2012 , robot , IEV , Oski , Rubik's Cube , Formal verification , IFV , cloud computing , verification

Using Event Ports (With Edge Attribute) to Define Simulator Sensitive Events Rather…

There are two ways in e to define an event to be sensitive to a change of value in…

• 6 min read
AF , events , Specman , Synchronization , Functional Verification , event ports , ports , simple ports , e language , team specman , interface , edge attribute

DAC 2012: Connecting Emulation to the Real World of Wireless Interfaces

This is certainly the most connected DAC I have been to so far. Tweets and connections…

• 2 min read
ESL Market , DAC , wireless , Verification Computing Platform , Virtual System Platform , software virtual prototype , cadence , Acceleration , Functional Verification , Palldium XP , System Design and Verification , System Development Suite , system modeling , embedded software , Rohde & Schwarz , Emulation , dac2012 , LTE , Design Automation Conference , carrier aggregation , LTE advanced

DAC 2012: High-Level Synthesis Tutorial Standing Room Only

Monday is tutorial day at DAC, and this year the highest-attended tutorial was Synthesizing…

• less than a min read
High-Level Synthesis , Intel , C to Silicon , dac2012 , Bohm , SystemC , Synthesis , HLS , ESL , verification

DAC 2012 Gary Smith EDA Kickoff: EDA and ESL Growth and Four Different Software Virtual…

DAC 2012 kicked off yesterday with the annual DAC Reception followed by Gary Smith…

• 3 min read
ESL Market , DAC , Virtual System Platform , software virtual prototype , cadence , Functional Verification , System Design and Verification , Gary Smith EDA , System Development Suite , system modeling , embedded software , GSEDA , dac2012 , Design Automation Conference

DAC 2012: Handling a Double Paradigm Shift for Embedded Software Development

Change is hard. And we in product marketing for development tools are trying to cause…

• 4 min read
DAC , Virtual System Platform , CDNLive , cadence , debug , Functional Verification , Verum , System Design and Verification , Methods2Business , System Development Suite , system modeling , embedded software , dac2012 , Technology Adoption , Software Generation , Design Automation Conference , Formal verification

Accellera Systems Initiative Releases UVM 1.1b for SystemVerilog

Accellera Systems Initiive released the UVM 1.1b on its website June 1 and announced…

• less than a min read
DAC , uvm , uvm world , Functional Verification , UVM 1.1b , Accellera

Being The Energizer Bunny at DAC … Championing System-Level Design and Verification…

As the EDA industry and its customers are preparing for the yearly show down at the…

• 19 min read
NextOp , DAC , CDNLive , debug , Functional Verification , LeCroy , AMD , System Design and Verification , celeration , Methods2Business , System Development Suite , Xilinx SDK , Incisive , in-circuit emulation , LSI , Palladium XP , Emulation , in-circuit acceleration , Dini , Imperas , ARM , Design Automation Conference , Rohde&Schwarz , DAC breakfast

TLM Design and Verification: What to See at DAC This Year

If you are attending the Design Automation Conference ( DAC 2012 ) June 4-7 in San…

• 1 min read
High-Level Synthesis , DAC , TLM , C to Silicon , transaction level , tlm verification , System Design and Verification , TLM design , embedded software , ESLsyn , C-to-Silicon , SystemC , HLS , NASCUG , ESL

Using Physical USB Devices with the Xilinx Zynq-7000 Virtual Platform

There are two choices for how to handle USB devices in a virtual platform. A USB…

• 4 min read
Virtual System Platform , virtual platforms , virtual prototypes , embedded software , USB , Zync-7000 , SystemC , physical USB devices , xilinx , linux , QEMU , System Design and Verification

Tips on Writing Macros in Specman e Language

In this blog, I will present some tips that can be very useful when you write e macros…

• 4 min read
AF , Specman , Functional Verification , Incisive , e language , define-as , writing macros , macros , testbench , simulation , verification

How Debug Breakthroughs are Enabled by In-Circuit Acceleration

We in product management are often accused of jumping the gun and announcing products…

• 5 min read
DAC , CDNLive , Acceleration , debug , Functional Verification , AMD , System Development Suite , Incisive , in-circuit emulation , Palladium XP , Emulation , in-circuit acceleration , Design Automation Conference , DAC breakfast , System Design and Verification

The Facts: Why Accelerated VIP Is Needed for SoC Verification

On Tuesday May 15 th Cadence announced the expansion of our VIP Catalog to include…

• 4 min read
AVIP , SystemVerilog , accelerated VIP , Verification IP , uvm , Acceleration , Functional Verification , VIP , Palladium , Palladium XP , Emulation , VIP Catalog , simulation VIP , ACE verification , e language , SCE-MI , SystemC , protocol verification , simulation , verification

American Technology Awards - Finally I Can Explain to my Mom What I am Actually Working…

I think all of us engineers have faced at one point or another the need to explain…

• 2 min read
Rapid Protoytping Platform , Virtual System Platform , virtual platforms , awards , Watson , virtual prototypes , American Technology Awards , Jeopardy , System Development Suite , VSP , Incisive , Palladium XP , Raritan , Mother's Day , System Design and Verification , cloud computing , FPGA-based prototyping

DAC 2012 Preview: Focus on Formal and ABV Events and Papers

In a few short weeks DAC 2012 will be upon us (June 3-7, 2012 in San Francisco, CA…

• 2 min read
DAC , Incisive Formal Verifier , ABV , Functional Verification , Formal Analysis , formal , "Coverage Unreachability" , coverage unreachability , formal apps , model checking , bypass verification , apps , Lego , User Track , assertions , papers , DAC 2012 , robot , IEV , Design Automation Conference , Rubik's Cube , IFV , Assertion-based verification

Specman’s Memory Management Orientation Guide (or “Honey – Please Take out the Garbage…

Memory management is not something the Specman user is supposed to worry about. Nobody…

• 9 min read
AF , Specman , Memory , garbage , Functional Verification , garbage collection , Specman garbage collection , Incisive , e language , managing memory , Specman data , memory errors , testbench , simulation , memory management , verification

Video Tech Tip: Data Path Verification Using a Formal Scoreboard with Incisive Formal…

This 6 minute video is a quick overview of our formal scoreboard app. Specifically…

• less than a min read
scoreboard , ABV , Joerg Mueller , Formal Analysis , formal , video , formal apps , apps , formal scoreboard , IEV , IFV

Xilinx Zynq-7000 Virtual Platform Performance: Native Linux vs. VirtualBox

In my last blog post , I covered three frequently asked questions about using the…

• 5 min read
taskset , virtual platforms , Unity 2D , System Development Suite , embedded software , VSP , Ubuntu , VirtualBox , virtual prototype , Virtual Machine , Linux vs VirtualBox , Unity3D , xilinx , graphics , linux , Zynq-7000 , simulation , ESL , System Design and Verification

Xilinx Zynq-7000 Virtual Platform Frequently Asked Questions: VirtualBox Edition

The use of virtual machine technology offers great ease of use benefits. Since the…

• 7 min read
VBoxManage , port forwarding , network address translation , eclipse , virtual platforms , NAT , virtual prototypes , embedded software , Xilinx SDK , Ubuntu , VirtualBox , system design , Virtual Machine , FAQ , System Design & Verification , xilinx , Zynq virtual platform , Zynq-7000 , ESL

My Constraint was Ignored – Is it a Tool Bug? IntelliGen Gen Debugger Can Help!

The IntelliGen Gen Debugger is a powerful Specman tool that can debug any generation…

• 4 min read
AF , IntelliGen , Specman , debug , Functional Verification , Gen debugger , test generation , Gen , Generation , e language , Constraints , constraint not enforced , verification

Analyzing Error Reports When Specman Crashes

One of the most frustrating events while running a tool would be to experience a…

• 8 min read
AF , SystemVerilog , Specman , OVM ML , Functional Verification , Testbench simulation , OVM e , EDA , e , stack trace , Signal Integrity , e language , team specman , Aspect Oriented Programming , eRM , specman crashes , simulation , AOP , IES-XL

Video: “Drive For Innovation” Finds It At Every Turn

With some notable exceptions, too often technology trade press reporting has been…

• less than a min read
Brian Fuller , Avenet Express , Joe Hupcey III , innovation , "Drive for Innovation" , UBM Electronics , Chevy Volt , EE Times

Modeling Large Memories in SystemC

Sometimes Virtual Platforms model systems with large amounts of memory. Many embedded…

• 3 min read
zynq , Memory , virtual platforms , TLM , virtual prototypes , SDRAM , Verilog , SystemC memories , SystemC , memory models , modeling memories , linux
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