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Why LLMs Are the Best Thing to Happen to Chip Design

By Kartik Hegde, Sr. Engineering Group Director We live in a world increasingly…

Corporate
• 7 min read
featured , chip design , AGI , LLMs

Shift Verification Left: AI Tools for Faster, Smarter Chip Design

Originally written by Hamid Shojaei, Co-Founder of ChipStack and now Distinguished…

RobbieOSullivan
• 7 min read
ChipStack , featured , EDA , ChipStack AI Super Agent , AI

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium
Verification
Latest blogs

Ubuntu 12.10 on a Virtual Platform at ARM Techcon

Next week (Oct. 30-Nov. 1) ARM TechCon 2012 is at the Santa Clara Convention Center…

• 1 min read
ARM Techcon , Virtual System Platform , virtual platforms , programmer's guide , virtual prototypes , Cortex-A9 , Cortex-A , VSP , Ubuntu , ARM , Quantal Quetzal , Ubuntu 12.10 , linux , Jason Andrews , Zynq-7000

Margins are Costly - Don't Let Them Grow Out of Control!

Last week, Professor Jan Rabaey of the University of California at Berkeley gave…

• 2 min read
High-Level Synthesis , Low Power , Rabaey , low power summit , margins , rtl compiler , variability , C-to-Silicon Compiler , HLS

Changing the Game with Processor Based Emulation

I have always been fascinated by game changing moves. Some are more successful than…

• 7 min read
RPP , FPGA Based Prototyping , prototyping , cadence , Acceleration , debug , Functional Verification , System Design and Verification , Palladium , System Development Suite , embedded software , Emulation , Software Development and Debug , Rents Rule , Schirrmeister , system integration , FPGA

UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar

Every SoC project uses multiple languages. Even if the design itself is purely Verilog…

• 1 min read
IEEE 1647 , SystemVerilog , uvm , IEEE 1800 , UVM-ML , Functional Verification , OVM , e , webinar , UVM ML , multi-language , Accellera , SystemC , multi-language UVM , IES , IES-XL

Recorded Webinar: Using Metric-Driven Verification and Formal Together For Higher…

[Preface: the upcoming " Club Formal " on October 17 here at the Cadence San Jose…

• 3 min read
coverage , Functional Verification , Metric Driven Verification , Formal Analysis , formal , Incisive , webinar , Incisive Enterprise Verifier , Chris Komar , enriched metrics , MDV , IEV , debugging , John Brennan , simulation , Formal verification , IFV

Using pli_access for Stubless Indexed Ports

Indexed ports are used to access composite HDL objects in SystemVerilog (SV). Their…

• 3 min read
AF , indexed ports , SystemVerilog , stub files , Specman , stubless indexed ports , Functional Verification , ports , Nir Hadaya , SV , e language , interface , simulation , Avi Farjoun

Shameless Promotion: Free Club Formal San Jose (with Lunch) on Wednesday 10/17

Please join Team Verify and other design and verification engineers at the next …

• 1 min read
ABV , Formal Analysis , formal , formal apps , Vigyan Singhal , Chris Komar , Oski Technology , Club Formal

iPhone5 Differentiation is Chip Design

In case you may have missed it, Apple recently launched a new iPhone. As per the…

• 5 min read
High-Level Synthesis , Apple , TLM , RTL , android , iPhone5 , Samsung , SoC , C-to-Silicon , software , smartphones , ARM , ESL , iPhone , Audience

Using a Network File System with the Xilinx Zynq-7000 Virtual Platform

There are a number of ways to do embedded software development for Xilinx Zynq-7000…

• 5 min read
Ubuntu 12.04 , Zynq virtual platform , Network File System , Embedded Linux

Accelerated VIP Delivers Value for Firmware/Driver Validation and Integration

Earlier this year, Cadence announced the expansion of its VIP Catalog to include…

• 2 min read
validation. , Driver , firmware , System Design & Verification

Lessons for EDA When Low Power vs. Heat Dissipation Isn’t a Fair Fight: A Case Study…

Right up there with functional verification, the challenges of low power design and…

• 3 min read
uvm , Low Power , GoPro Hero2 , thermal verification , Functional Verification , MCAD , video , mechanical design automation , EDA , low-power design , thermal behavior , heat dissipation

UVM Testflow Phases, Reset and Sequences

In this post, we will discuss the interesting challenge of reset during simulation…

• 2 min read
AF , uvm , Specman , BFM , Testflow , Functional Verification , testflow phases , e language , team specman , sequences , Reset mechanism , Shneydor , verification , sequence driver

What Does it Take to Migrate from e to UVMe?

So you are developing your verification environment in e , and like everyone else…

• 3 min read
IEEE 1647 , SystemVerilog , scoreboard , uvm , Specman , Specman/e , UVM e , vr_ad , UVM-e , advanced verification , e language , UVC , SCE-MI , team specman , Constraints , Aspect Oriented Programming , sequences , Incisive Enterprise Simulator (IES) , Shneydor , AOP

Introduction to the Linux Kernel Message System

One of the most common problem reports related to Virtual Platforms running Linux…

• 6 min read
Virtual System Platform , virtual platforms , GDB , VAP , cadence , ring buffer , uncompressing Linux , virtual prototypes , booting Linux , embedded software , VSP , Imperas , software development , Zynq virtual platform , linux , Zynq-7000 , Embedded Linux , ESL , System Design and Verification , kernel messaging system , Andrews

Report From Silicon Valley With Application Engineer Bin Ju

Luckily I was able to track down my very busy colleague Bin Ju between assignments…

• less than a min read
Joe Hupcey III , ABV , Formal Analysis , Bin Ju , formal , video , formal apps

Improving SimVision Fonts for Ubuntu

This article is a follow-up on an early 2012 article about using Incisive and Virtual…

• 4 min read
Virtual System Platform , virtual platforms , System Design and Verification , VSP , Incisive , Ubuntu , Ubuntu 12.04 , SystemC

A “Reflection” on Chip-Level Debugging with Specman/e and SimVision

Last week, a favorite customer of mine called me in a panic, just days from tape…

• 6 min read
Specman , Specman/e , debug , simvision , Incisive , SimCompare , e language , chip-level debugging , Funcional Verification , reflection , irun , testbench , simulation

SimVision Watch Window Now Accommodates Specman Watch Items

Starting from version 12.1, the SimVision Watch Window accommodates Specman watch…

• less than a min read
AF , Specman , gui , watch window , debug , Functional Verification , specview , Specman watch , simvision , SimVision watch window , watches , Chudnovsky

Video: Interview with Professional Teenage Technology Coach Kristine Bonhoff

Over the past several years at various EDA trade events, one of the more popular…

• 1 min read
Joe Hupcey III , Kristine Bonhoff , interview , video , EDA360 , apps , teen tech

Product Update: New Assertion-Based Verification IP (ABVIP) Available Now

Verifiers rejoice: R&D has just released all-new Assertion-Based Verification IP…

• 2 min read
Incisive Formal Verifier , Jose Barandiaran , ABV , Functional Verification , ABVIP , formal , formal apps , assertions , IEV , Incisive Enterprise Simulator (IES) , Formal verification , IFV , verification , Assertion-based verification , IES-XL

Video: DVCon 2012 Digital-Mixed Signal (DMS) Expert Neyaz Khan on UVM Mixed Signal…

E-mail reminders for the DVCon 2013 Call For Abstracts prompted me to look through…

• 1 min read
digital mixed-signal , AMS , uvm , Joe Hupcey III , verification strategy , Verification methodology , Functional Verification , UVM-MS , Neyaz Khan , Mixed Signal Verification , Mixed-Signal , DVcon , Maxim Semiconductor , verification

My Constraint was Ignored – Is it a Tool Bug? – Part 2

In a previous post we showed some cases of user code that can cause ignored constraints…

• 3 min read
AF , IntelliGen , Specman , debug , Functional Verification , Generation , e language

UVM Testflow Phase Debugging- Identifying Blocking Activities

UVM Testflow debugging capabilities have been recently enhanced through the addition…

• 1 min read
AF , uvm , Specman , methodology , Testflow , Functional Verification , testflow phase debugging , testflow phases , advanced verification , e language , blocking activities , IES-XL

Adding Xilinx C Models to the Virtual Platform of the Zynq-7000 EPP

Today, I have a good article from Henry Von Bank of Posedge Software related to Zynq…

• 5 min read
Virtual System Platform , zynq , virtual platforms , TLM , posedge , IP-XACT , Henry Von Bank , virtual prototypes , VSP , RDF , SystemC , xilinx , ARM , FFT , Zynq virtual platform , Zynq-7000

Using Flexible Specman License Searches

Until recently, Specman used to look for its licenses in the following strict, hardcoded…

• 2 min read
AF , Specman , new features , Functional Verification , licenses , license search , Incisive , e language , Specman licenses , verification , IES-XL

DAC 2012 Video: Dr. Kerstin Eder, University of Bristol, About Her Course on Functional…

Dr. Kerstin Eder, a Senior Lecturer in the Computer Science department at the University…

• 1 min read
DAC , uvm , Joe Hupcey III , interview , Functional Verification , video , Dr. Kerstin Eder , University of Bristol , DAC 2012

C-to-Silicon Japan User Group and Ikegami Production Experience

We have been seeing some rapid growth in adoption of C-to-Silicon Compiler high-level…

• 2 min read
High-Level Synthesis , customers , Maesato , japan , Japan user group , Ikegami , SystemC , C-to-Silicon Compiler , Synthesis , Virtex-6 , HLS , ESL , FPGA

Video: DAC 2012 Update on AMIQ’s DVT IDE – New RTL Design Work Flow Support

Readers of this blog and of Team Specman will recall that Integrated Development…

• less than a min read
DAC , eclipse , Joe Hupcey III , Cristian Amitroaie , DVT , AMIQ , DAC 2012 , RTL design , integrated development environment , IDE
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