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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification

Latest blogs

Video: Meet Formal and ABV R&D Team Leader Deepak Pant

Inspired by the positive response to my interview of Formal R&D Distinguished Engineer…

• less than a min read
Alok Jain , ABV , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , Deepak Pant , video , ADS , assertions , IEV , Formal verification , IFV , Assertion-based verification

How Will High-Level Synthesis Affect the Make vs. Buy vs. Re-use Decision?

During the planning phase for SoC designs, teams have to choose whether to "make…

• 2 min read
High-Level Synthesis , IP , TLM , System Design and Verification , C-to-Silcon , IP re-use , re-use , reuse , SystemC , C-to-Silicon Compiler

Will Software Development Cause Another “Industrial” Revolution?

As you have read here before, Cadence has been working closely with Xilinx to create…

• 3 min read
zynq , edaForum , virtual prototypes , industrial , System-Level Design , Siemens , Virtual Platforms , Industrial Automation , Design Flows , Sanitas

India Needs Real-World Assertions Too

I've just returned from a week-long trip to India, spending most of my time at the…

• 4 min read
Functional Verification , Old Delhi , Noida , assertions , New Delhi , real-world assertions , India

Parallel Compilation for SystemC

One of the most common complaints about SystemC is that it takes too long to compile…

• 3 min read
Virtual System Platform , virtual platforms , GNU , parallel compilation , virtual prototypes , embedded software , C , LSF , compile , pallallel compile , make , SystemC , System Design and Verification

Event Report: Club Formal Shanghai

The first "Club Formal" event in China was held in Shanghai on Oct. 21 2011, and…

• 2 min read
events , Verification IP , China , ABV , verification strategy , Functional Verification , ABVIP , formal , ADS , assertions , Club Formal , IEV , Assertion-Driven Simulation , Shanghai , Formal verification , IFV , Jin Tang , Assertion-based verification

Report on CDNLive! India 2011: Provocative Keynotes, Detailed Papers, and Robots…

Recently I had the honor of presenting the functional verification roadmap at CDNLive…

• 2 min read
Suman Ray , Low Power , Joe Hupcey III , ABV , Apurva Kalia , verification strategy , CDNLive , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , Manu Chopra , Incisive , Lokesh Pundreeka , SVA , Lego , assertions , robot , MDV , Rubik's Cube , Formal verification , IFV , Assertion-based verification

Shameless Promotion: Free Club Formal San Jose, Formal Scoreboard Webinar

Please join Team Verify and other D&V engineers for one or both of the following…

• 1 min read
scoreboard , ABV , methodology , verification strategy , Joerg Mueller , Functional Verification , Formal Analysis , formal , EDA360 , webinar , Club Formal , IEV , Formal verification , IFV , Assertion-based verification

Welcome to the Zynq-7000 Virtual Platform

As you might guess we are pretty excited about the Virtual Platform development for…

• 4 min read
zynq , virtual platforms , TLM , EPP , Zynq-7000' , virtual prototypes , Cortex-A9 , System Design and Verification , software , SystemC , xilinx , ARM , linux , extensible , FPGA

Verification and the Need for Collaboration

Earlier this week I was at the ARM TechCon in Santa Clara, a show that gets better…

• 2 min read
NextOp , ARM Techcon , uvm , collaboration , Zocalo , Functional Verification , Standards , partnerships , VA , EDA360 , EDA , Duolog , verification alliance , UCIS , AMIQ

Report: Formal Analysis Papers at CDNLive India 2011

On October 19, 2011 in Bangalore, India more than 800 engineers across all domains…

• 3 min read
ABV , CDNLive , Functional Verification , Formal Analysis , ABVIP , formal , Lokesh Pundreeka , ADS , metric-driven verification , assertions , MDV , IEV , Assertion-Driven Simulation , Formal verification , IFV , India , Assertion-based verification

Virtual Platform UART Use Number 4: Connecting to an RTOS Tracing Framework

This is the last installment of my series on different uses for the UART in Virtual…

• 4 min read
Virtual System Platform , virtual platforms , Quantum Platform , virtual prototypes , dining philosophers , UART , System Design and Verification , RTOS tracing , QP , software , qspy

Come See How to Connect SystemVerilog and SystemC Using UVM

All pun-tastic references aside, connecting SystemVerilog and SystemC is becoming…

• 1 min read
SystemVerilog , uvm , OVM ML , Functional Verification , webinar , multi-language , SystemC , IES

Too Many Missing Real-World Assertions?

Well, here I am embarking on my fifth post in which I point out illogical situations…

• 4 min read
ABV , Functional Verification , formal , assertions , Assertion-based verification

Formal Verification with Asynchronous Clocks

Many designs have multiple independent clock inputs with different frequency specifications…

• 2 min read
ABV , asssertion-based verification , Joerg Mueller , Verification methodology , Functional Verification , Formal Analysis , formal , SVA , PSL , assertions , IEV , Formal verification , IFV , verification

Automating UVM to Tackle Insidious HW/SW Bugs

You've just sat through a 2-hour program review. The 30 minutes you spent describing…

• 1 min read
SystemVerilog , uvm , bugs , Duolog , universal verification methodology , Accellera VIP TSC , David Murray , IES

Free Webinar Thursday 10/13 -- Automating Assertion Generation for Simulation, Formal…

Everyone can agree that Assertion-Based Verification (ABV) is a powerful methodology…

• 1 min read
NextOp , Joe Hupcey III , ABV , methodology , interview , Formal Analysis , BugScope , Incisive , webinar , DVcon , assertion synthesis , assertions , IEV , Yuan Lu , Formal verification , IFV , Assertion-based verification , IES-XL

17M Gates in 8 Months with 2 Designers -- What is Your ROI for Higher-Abstraction…

In their presentation at the recent SystemC Japan conference, Renesas Micro Systems…

• 3 min read
time-to-market , High-Level Synthesis , verification turnaround , TLM , C-to-Silcon , ROI , System-Level Design , SystemC , C-to-Silicon Compiler , productivity

Amazon’s New Kindles: More Steps Toward the Paperback Computer

While I understand that a new Kindle Fire at $199 MRSP is significantly more than…

• 4 min read
Verification IP , RPP , SaaS , Joe Hupcey III , paperback computer , Cadence VIP portfolio , Kindle , system realization , VIP , EDA360 , EDA , VSP , Palladium XP , tablet , Hosted Design Solutions , Jim Hogan , Rapid Prototyping Platform , Amazon , Steve Leibson , cloud computing

Technical Tip on How to Use HDL Assertions in e

While assertion callbacks have existed in Specman/e for several years now, several…

• 2 min read
IntelliGen , Specman , Incisive Enterprise Simulator , Incisive , e , SVA , e language , team specman , OOP , assertions , eRM , simulation , AOP , verification , Assertion-based verification

edaForum: Evolving Devices from “All in One” to “One for All”

This week I had the pleasure to attend and to present at the 11th annual edaForum…

• 7 min read
PCB , IMC , Intel , virtual platforms , edaForum , virtual prototypes , IP integration , System Development Suite , EDA360 , embedded software , Shirrmeister , IC/package co-design , one for all , hardware/software co-development , Power Analysis , System Design & Verification , Frank Schirrmeister , all in one , Eul , power , debugging , System Design and Verification

Missing Real-World Assertions in Computer-Land

I was reviewing the page view statistics on the Cadence Functional verification…

• 3 min read
uvm , ABV , outlook , Functional Verification , formal , assertions , Assertion-based verification

Virtual Platform UART Use Number 3: Using gdb to Debug a Software Application

This is the next installment in my series covering the uses of the venerable UART…

• 7 min read
virtual prototoypes , virtual platforms , TLM , GDB , debug , UART , embedded software , software , SystemC , debugging , linux , System Design and Verification

ARM/Cadence Video: How ACE Coherency Adds Value and Verification Complexity

The number of licensees for ARM's Cortex-A15 CPU core is growing rapidly, particularly…

• 1 min read
Verification IP , ACE , Cortex-A15 , Functional Verification , video , VIP , interconnect monitor , ACE verification , cache coherency , coherency , ARM

Tech Tip: The “Show Me” Witness Trace Short-Cut for Design Bring-Up

In a prior Team Verify post, Application Engineer Bin Ju talked about several applications…

• 1 min read
show me , ABV , Functional Verification , Formal Analysis , formal , ADS , Chris Komar , witness trace , IEV , Assertion-Driven Simulation , simulation , Formal verification , IFV , Assertion-based verification

Rumors of SystemVerilog’s Death Have Been Greatly Exaggerated

Our friend and fellow blogger JL Gray recently published a post with the provocative…

• 2 min read
SystemVerilog , uvm , uvm world , universal verification methodology , UCIS , Accellera , JL Gray

Everything New is Old … Everything Old is New

The title of this post is taken from a fairly obscure 1982 record album (yes, vinyl…

• 2 min read
gate level , Functional Verification , LEC , RTL , DRC , LVS , EDA , old , gate-level , new , simulation

Virtual Platform UART Use Number 2: Using telnet to Connect to a UART

Welcome to the next installment in my series about different ways to use the venerable…

• 4 min read
Virtual System Platform , TLM , virtual platform , UART , System Design and Verification , telnet , embedded software , xterm , virtual prototype , software , SystemC , linux , ESL
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