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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification

Latest blogs

Can Your Verification Survive “Boot Camp”?

In Silicon Valley there is a popular fitness program called "Boot Camp" where people…

• 1 min read
ABV , boot camp , Functional Verification , Formal Analysis , formal , Incisive , assertions , IEV , Assertion-Driven Simulation , Formal verification , IFV , Assertion-based verification

What Does SystemC Mean for Design and Verification?

My colleague Jack Erickson recently published in the Cadence System Design and…

• 3 min read
Virtual System Platform , TLM , uvm world , Functional Verification , Incisive Enterprise Simulator , VSP , C-to-Silicon , SystemC , IES-XL

If Only Carl Friedrich Gauss had IntelliGen in 1850

The N-queens issue is a challenging but standard puzzle when it comes to the world…

• 5 min read
N-queens , IntelliGen , Specman , Object Oriented Programming , Functional Verification , Testbench simulation , e , OVM-e , team specman , specman elite , multi-language , Gauss , simulation , Rubik's Cube , AOP , Trailblazer

Virtual Platform UART Use Number 1: Connecting to an Interactive Terminal

Welcome to the first example of using a UART in a Virtual Platform. For those just…

• 8 min read
Virtual System Platform , virtual platforms , Embecosm , virtual prototypes , UART , System Design and Verification , System Development Suite , xterm , SystemC

UCIS Coverage Standard -- Innovation Means Business

Open solutions are just curiosities until the ecosystem figures out how to turn…

• 1 min read
metric-driven , coverage , Functional Verification , Metric Driven Verification , EDA360 , Incisive , Enterprise Manager , Plan and metrics management , UCIS , Accellera , coverage driven verification (CDV) , MDV

What I Learned Traveling Across the Silicon Prairie

Inspired by Brian Fuller's cross-country "Drive for Innovation" , last week I jumped…

• 1 min read
Silicon Prarie , Joe Hupcey III , ABV , Functional Verification , Formal Analysis , formal , ADS , IEV , Assertion-Driven Simulation , Formal verification , IFV , Assertion-based verification

Verifying AMBA® 4 ACE Designs – Cadence is Ready to Help, Now

ACE is here. Are you ready? Designers of multimedia smartphones, tablets, and other…

• 1 min read
Verification IP , ACE , Functional Verification , VIP , tablet , AMBA , Smartphone , EE Times

IP Cannot be an Efficient Abstraction Level Without SystemC!

EDN recently featured a lengthy article entitled " SOCs: IP is the new abstraction…

• 3 min read
High-Level Synthesis , IP , TLM , RTL , abstraction , IP re-use , EDN , SoC , IP assembly , system design , SystemC , HLS , System Design and Verification

Virtual Flash Memory Gets Real

This week's Flash Memory summit will not only highlight the IP Cadence delivers,…

• 1 min read
Virtual System Platform , IP , Memory , virtual platforms , TLM , virtual prototypes , TLM 2.0 , flash memory , Incisive Software Extensions , ISX , Flash Memory Summit , System Design and Verification

A Must Read: the ARM Cortex-A Programmer's Guide

For the last couple of years, I have been getting a lot of e-mail from different…

• 2 min read
ARM Cortex-A , virtual platforms , programmer's guide , virtual prototypes , Cortex-A , virual platform , ARM Architecture , ARM , linux , System Design and Verification

The Return of the Son of Real-World Assertions

I've received some nice feedback on my previous two posts about real-world situations…

• 3 min read
ABV , Functional Verification , formal , assertions , Assertion-based verification

Four Uses for the Venerable Virtual Platform UART

The Universal Asynchronous Receiver/Transmitter (UART) is one of the oldest hardware…

• 2 min read

Some Reflections on the Development of UVM World

In a recent blog post , I celebrated our donation of the Cadence-developed UVM…

• 3 min read
uvmworld.org , uvm , uvm world , Functional Verification , OVM , universal verification methodology , Accellera , verification

ARM Generic Interrupt Controller HOWTO

Way back in 2004, I wrote a book called Co-Verification of Hardware and Software…

• 5 min read
Virtual System Platform , Cortex-A9 , System Design and Verification , Cortex-A , howto , ARM Generic Interrupt Controller , SystemC , GIC , ARM , Wadikar , Generic Interrupt Controller

Video: Discussion with EET’s Brian Fuller on EDA, Engineers, and Social Media

At DAC I had the honor of being interviewed by EE Times editor Brian Fuller on my…

• 1 min read
Brian Fuller , DAC , Joe Hupcey III , tweeting , videos , interview , Blogging , YouTube , blogs , Facebook , OrCAD , CtoSilicon , Twitter , Social Media , EE Times , DAC360

Enterprise Planner - CSV Import Tech Tip

Are you interested in an automating your directed or random test list that you manually…

• 1 min read
metric-driven , Functional Verification , Metric Driven Verification , CSV , vPlan , tech tips , EDA360 , Incisive , Enterprise Manager , Enterprise Planner , MDV , Excel , verification

Creating SystemC TLM-2.0 Peripheral Models

Over two years ago, I made some experiments and raised some requirements for an effective…

• 8 min read
Virtual System Platform , virtual platforms , TLM , IP-XACT , Models , virtual prototypes , System Design and Verification , TLM 2.0 , embedded software , VSP , TLM-2.0 , Team ESL , peripheral , SystemC , ESL

More Examples of Missing Real-World Assertions

Back in May, I published a blog post with examples of real-world situations that…

• 3 min read
ABV , asssertion-based verification , Functional Verification , formal , assertions

Celebrating the Success of the UVM World Web Site

In case you missed it, Cadence issued a press release last week announcing that we…

• 2 min read
uvm , uvm world , universal verification methodology , Accellera

True Stories of Assertion Driven Simulation (ADS) in the Wild

Ever since Assertion-Driven Simulation (ADS) became available, I have been working…

• 4 min read
AXI , ABV , Verification methodology , Functional Verification , Formal Analysis , ABVIP , formal , simvision , VIP , ADS , DDR , Club Formal , Constraints , IEV , Assertion-Driven Simulation , Formal verification , Assertion-based verification

Video: Distinguished Engineer Mike Stellfox on UVM, the Debug Bottleneck, and System…

My colleague and Cadence Distinguished Engineer Mike Stellfox leads a group of trailblazers…

• less than a min read
DAC , uvm , debug , system realization , Mike Stellfox , Accellera , SystemC , Trailblazer

Before DAC, There Was Club Formal – An Event Series Completely Focused on Formal…

To complement our support of DAC, CDNLive, and other large-scale events, where the…

• 1 min read
events , ABV , verification strategy , Functional Verification , Formal Analysis , formal , Incisive , Incisive Seminar , ADS , Oski Technology , Silicon Realization , assertions , Club Formal , ClubT , IEV , Assertion-Driven Simulation , Formal verification , IFV , verification , Assertion-based verification

Full Sequence Coverage in a Single Line of e Code?

I was asked recently about how to easily collect coverage on the sequences generated…

• 1 min read
Specman , e , OVM-e , e language , team specman , specman elite , AOP

Video: Duolog at DAC 2011 Update – Automating Design and Verification IP Integra…

One of the key tenants of the EDA360 vision is the need for scalable, correct-by…

• 1 min read
Cadence Connections , DAC , uvm , Virtual System Platform , IP , videos , IP-XACT , TLM 2.0 , VIP , EDA360 , Duolog , Incisive , Socrates , AMBA , ARM , David Murray

Video: DAC 2011 Update From NextOp CEO Yunshan Zhu

At DAC 2011 I had the opportunity to reconnect with Yunshan Zhu, the CEO of NextOp…

• less than a min read
Cadence Connections , NextOp , DAC , uvm , ABV , Yunshan Zhu , verification strategy , Functional Verification , Formal Analysis , BugScope , assertion synthesis , assertions , Design Automation Conference , Formal verification , verification , Assertion-based verification

Planes, Trains and Automobiles: European Seminar Series

A couple of blog posts ago, I talked about the worldwide functional verification…

• 3 min read
Functional Verification , Europe , formal , Incisive , Mixed-Signal , EMEA , metric-driven verification , MDV , IEV , IFV

Video: Update on AMIQ’s DVT IDE at DAC 2011 – Specman Debugger Integration, Open…

Specmaniacs and IES-XL users around the world know that Integrated Development Environment…

• less than a min read
DAC , eclipse , uvm , Specman , Functional Verification , Amitroaie , OVM , e , DVT , e language , AMIQ , eRM , IDE , verification , IES-XL

Video: Formal Verification Service Provider Oski Technology at DAC 2011

At DAC 2011, both myself and fellow Team Verify member Tom Anderson felt a distinct…

• 1 min read
DAC , ABV , verification strategy , Verification methodology , Functional Verification , Formal Analysis , formal , Oski Technology , assertions , Formal verification , verification , Assertion-based verification
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