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Why LLMs Are the Best Thing to Happen to Chip Design

By Kartik Hegde, Sr. Engineering Group Director We live in a world increasingly…

Corporate
• 7 min read
featured , chip design , AGI , LLMs

Shift Verification Left: AI Tools for Faster, Smarter Chip Design

Originally written by Hamid Shojaei, Co-Founder of ChipStack and now Distinguished…

RobbieOSullivan
• 7 min read
ChipStack , featured , EDA , ChipStack AI Super Agent , AI

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium
Verification
Latest blogs

Hate Writing Assertions? No problem: let Automatic Formal Analysis do the work

OR: “Leverage automatic checks extracted from designs without writing a single assertion…

• 4 min read
ABV , Functional Verification , Formal Analysis , formal , Incisive , IEV , IFV

New Blog: All About Integrated formal, Simulation, and Assertion-Based Verification…

End-users of Incisive Formal Verifier ("IFV"), Incisive Enterprise Verifier ("IEV…

• 1 min read
ABV , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , OVM , Incisive , Twitter , MDV , IEV , IFV

When Less Is More, Part 2: Is e Code Really Up to 3x More Compact Than SystemVerilog…

In my last post I wrote some packet generation code to validate the claim that e…

• 4 min read
IEEE 1647 , SystemVerilog , Functional Verification , OVM , OVM e , CDV , OVM SV , e , coverage driven verification (CDV) , Aspect Oriented Programming , AOP , IES-XL

When Less Is More, Part 1: Is e Really Up to 3x More Compact Than SystemVerilog?

A famous expression in the software world is that “you can only expect 10 good lines…

• 3 min read
IEEE 1647 , SystemVerilog , Object Oriented Programming , Functional Verification , OVM , OVM e , OVM SV , e , OOP , ClubT , Aspect Oriented Programming , AOP , IES-XL

Accessing Physical Memory and Registers in a Virtual World

When working with Virtual Platforms that are running operating systems it's sometimes…

• 3 min read
Registers , Memory , virtual platforms , Virtual , System Design and Verification

Tweeting From a Standards Meeting: Good or Bad?

In my last blog entry , I mentioned that I was able to keep up with a lot of the…

• 2 min read
uvm , tweeting , meetings , Functional Verification , texting , Accellera , EMAIL

Free eVC Generator From CFS Vision Update

In an earlier post Team Specman had the pleasure of introducing the free, open source…

• less than a min read
Specman , Functional Verification , OVM e , e , CFS Vision , FOSS , eRM

Crises In The Semiconductor Industry

I am on my way to Japan and I have just finished to read an excellent book and in…

• 2 min read
System Design and Verification , SoC , Semiconductor , ESL

Built-in Message Logging – Part 2 of 2

[Team Specman welcomes back guest blogger, Michael Avery from our Services Group…

• 3 min read
Specman , debug , Functional Verification , e , Funcional Verification , Aspect Oriented Programming , AOP

UVM = OVM 2.1: Even Better!

Since I'm not a member of the Accellera VIP TSC, I did not attend the 2.5-day face…

• 1 min read
uvm , Functional Verification , OVM , Accellera VIP TSC

Built-in Message Logging – Part 1 of 2

[Team Specman welcomes guest blogger Michael Avery, from our Services Group in the…

• 2 min read
Specman , Functional Verification , tech tips , e , AOP , IES-XL

VIP Portfolio Extension: New AMBA 4 Protocol Support

ARM-loving Specmaniacs's rejoice: we are now at liberty to announce that we are providing…

• 1 min read
metric driven verification (MDV) , Functional Verification , vPlan , Cadence VIP portfolio , OVM , VIP , Compliance Management System , CMS , AMBA , ARM

Have You Considered e Lately?

Richard Goering's recent interview with Mitch Weaver on the future of Specman and…

• 2 min read
SystemVerilog , Specman , Testbench simulation , e , verification

Running Incisive on Ubuntu Linux

Ubuntu is by many accounts the most popular and the easiest to use Linux distribution…

• 4 min read
Incisive , Ubuntu , Systemm Design and Verification , Virtual Machine , linux

Why OOP Falls Short For Verification

Last week at DVCon , frequent Team Specman guest blogger Matan Vax of R&D gave a…

• less than a min read
Object Oriented Programming , Functional Verification , e , DVcon , OOP , Aspect Oriented Programming , AOP

DVCon 2010 - Day 3

Click here or on the image below to go to the annotated photo blog of DVCon 2010…

• less than a min read
Object Oriented Programming , Functional Verification , OVM , OVM e , OVM SV , DVcon , OOP , AMIQ , OVM SC

DVCon 2010 Rocked!

I've spent much of this week at the San Jose Doubletree Hotel for DVCon 2010 , and…

• 1 min read
DAC , uvm , methodology , Functional Verification , OVM , DVcon

DVCon 2010 - Day 2

Click here or on the image below to go to the annotated photo blog of DVCon Day 2…

• less than a min read
Functional Verification , OVM , OVM e , CDV , OVM SV , e , Mike Stellfox , DVcon , OOP , AOP

DVCon 2010 - Day 1

Click here or on the image below to go to the photo blog of DVCon Day 1. …

• less than a min read
uvm , Functional Verification , OVM , OVM e , OVM SV , DVcon , AMIQ , Accellera , OVM SC

DVCon "Day 0" - Quick Report From SystemC Day

If you were looking for more evidence that the transition from RTL to ESL is gaining…

• 1 min read
TLM , Functional Verification , DVcon , SystemC , System Verification , ESL

Editor For OVM Field Registration Macros

The OVM SystemVerilog Class Library has built-in automation for many service routines…

• 1 min read
SystemVerilog , eclipse , uvm , Functional Verification , OVM , AMIQ , macros

DVCon: Showcasing The Cadence Passion For Verification Excellence

Yeah, I know I'm a marketing guy but I really like this stuff! For sure, we are going…

• 1 min read
SystemVerilog , uvm , Low Power , ABV , Functional Verification , simvision , OVM , Incisive , e , DVcon , SystemC , mixed signal , IES

Quiet Before The Storm? And What to Expect at DVCon 2010

In the last couple weeks Mentor did an about-face and decided to embrace SystemC…

• 1 min read
System Design and Verification , DVcon , SystemC , ESL

Rev 2 of OVM e Scoreboard on OVMWorld.org Now

Just in time for DVCon 2010 , I'm happy to inform you that revision 2 of the OVM…

• less than a min read
Functional Verification , OVM , OVM e , e , DVcon

Moving Past The Missing Model Syndrome

One of the issues that has hindered the progress of using Virtual Platforms for early…

• 4 min read
Fast Models , Models , virtual platform , C-to-Silcon , SoC , ARM , System Design and Verification

Cadence Exec: Why Cadence is Comitted to e/Specman

In case you or your management are wondering about Cadence's commitment to supporting…

• less than a min read
IEEE 1647 , SystemVerilog , IntelliGen , Specman , Object Oriented Programming , OVM ML , Functional Verification , OVM , OVM e , e , team specman , OOP , ClubT , Aspect Oriented Programming , SystemC , eRM , Incisive Enterprise Simulator (IES) , AOP , IES-XL , Trailblazer

OVM Community Contributions: Wildly Popular And Clearly Essential

A couple of weeks ago, before going to bed one night I checked the statistics for…

• 2 min read
uvm , Verification methodology , Functional Verification , OVM , Contributions , Accellera

DVCon 2010 For The Specmaniac

At next week's DVCon in San Jose, CA, Cadence will cover all aspects of our verification…

• 4 min read
SystemVerilog , Specman , TLM , Object Oriented Programming , OVM ML , Functional Verification , OVM , OVM e , Incisive , e , Mike Stellfox , DVcon , OOP , AMIQ , SystemC , MDV , eRM , AOP , IES-XL
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