IC Packagers: Transfer of IC Routing Blockage to Allegro Package Designer Route Keepout Using OrbitIO

A physical implementation designer may want to add a routing blockage on a chip or a package to optimize various aspects, such as signal integrity, power distribution, thermal management, or meeting manufacturing constraints. Typically, for signal integrity, these routing blockages can prevent noise that the signal paths would otherwise generate over a particular macroblock in a chip. By adding these blockages, the designer ensures that specific sensitive signals are kept away from potential aggressors such as high-speed signal lines, thereby reducing the risk of signal degradation and improving overall signal integrity.

If an IC designer has already defined such a routing blockage in the IC domain fabric, the package designer may want to leverage that information so as not to route above the same noise-sensitive block in the package domain fabric. But how can this information be smoothly transferred to the package domain fabric, considering the possible mirroring, rotation, and shrinking of the die against the package?

The post aims at guiding you through the process of transferring an IC routing blockage to build a route keepout in the package domain fabric.

Overview

The following figure outlines the routing blockage exchange between the IC design, OrbitIO Interconnect Designer, and Allegro Package Designer:

Transferring IC Routing Blockage to Allegro Package Designer Route Keepout

Routing blockage exchange between the IC design, OrbitIO Interconnect Designer, and Allegro Package Designer is a multi-step process as described in the following section:

Step 1: Importing LEF/DEF Files in OrbitIO Interconnect Designer

Read the information provided by the IC designer from the File – Import – LEF/DEF command.

Step 2: Creating New Macro in OrbitIO Interconnect Designer

Change the visibility for the Obstacles to 'On' to visualize the IC routing blockage in the OrbitIO canvas, as illustrated in the following image :

Run a few basic Java beanshell commands from the Commands and Messages window to retrieve the coordinates of the lower-left corner of the Obstacle, along with its height and width.

Create a new block in the die device with boundaries matching those of the Obstacle. Then, move it to overlap it with the existing routing blockage.

Step 3: Importing OrbitIO Database in Allegro Package Designer

Import the OrbitIO database into Allegro Package Designer because of the interoperability of Cadence products.

The package and die devices, along with the associated connectivity, are imported into Allegro Package Designer.

Step 4: Viewing IC Details

In Allegro Package Designer, view the internal details of the die using the Show IC Details command available in the Symbol Edit Application mode. You can, for example, see the I/O ring, the different macros placed within the die, or the RDL routing from the bumps to the I/O pads.

Step 5: Copying Routing Blockage Shape to Create Route Keepout

The shape corresponding to the routing blockage of the IC macro floorplan can be copied using the Z-copy command to create the needed route keepout. The die is already duly placed in the proper orientation (flipped and mirrored in this case, as this is a flip-chip device). You don’t have to perform tedious and error-prone calculations to place your route keepout properly in your design.

Step 6: Hiding IC Details

That's it! The shape is now available as a route keepout in the package domain fabric.

As a final step, run the Hide IC Details command in the Symbol Edit Application mode. You can continue routing packages with the appropriate route keepout to avoid routing above the noise-sensitive block in Allegro Package Designer.

Over to You

Do you want to try out this method? Do you want to delve deeper into the details of each step? Well, you can try out all the steps right away with a sample design using the Transferring a Routing Blockage from an IC Database to a Route Keepout in Allegro Package Designer Application Note available @ Cadence Online Support.

This AppNote was authored by Cadence Application Engineer, Jean-Francois Lepere.

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