Never miss a story from IC Packaging and SiP. Subscribe for in-depth analysis and articles.
Design reuse is the key to faster design cycles in today’s packaging design industry, where the shortest possible time to market makes or breaks the success of a product. As most of the package designs have wire bonding, sharing the wire bonding information across designs is of utmost importance. However, reuse and ECO (Engineering Change Order) of the designs can lead to wire bonding-specific package design issues that impact the design integrity and, at times lead to design failures in the later stages of the design process. The Cadence® Allegro® Package Designer Plus toolset provides robust checks to find such issues in a design and, wherever possible, resolves them automatically. This blog explores these wire bond-specific design integrity checks in detail.
To run the package design integrity checks in Allegro Package Designer Plus:
In the following illustration, many wire bond-specific package design integrity checks are highlighted. A DRC marker is shown at each instance. If you do not see DRC markers in the design canvas, ensure that DRC is enabled in the Visibility pane.
There are multiple ways to resolve these issues. The following design example uses some methods that I recommend:
Fixing Errors Automatically
One of the best and easiest methods is to let the application fix the errors automatically. In the Package Design Integrity Checks UI, enable the Fix errors automatically in the Package Design Integrity (where possible) option in the Reporting Options section, and click OK to run the checks and fix errors automatically.
This option cleans most of the wire bond-specific design issues, quickly and effectively.
Let’s see how to manually resolves some of the issues.
Fixing Dangling Bond Wires
In the example design, a few bond wires and their associated pins are on different nets. It happens when the die has ECO and connectivity changes and that are not propagated to the rest of the design. To remove these DRCs, choose Logic ─ Push Connectivity to propagate the connectivity from the die pins to the rest of the design. To know more about push connectivity, read How to Quickly Push Design Connectivity across a Design.
Fixing Pin Bond Wire Count
The example design has a VSS pin that is required to be connected to four bond wires to achieve a low inductance value. You can specify the wire bond number requirement by setting the WIRE_COUNT property on the pin. As you can see in the following image, only three bond wires are connected to the VSS pin, which is marked by a pointer.
One more wire bond must be connected to this pin to resolve the issue. To add an additional wire bond, use the Route ─ Wire Bond ─ Add command.
Fixing Power/Ground Ring Configuration
Another issue in the example design is that the VDD net does not have the correct voltage value assigned. To fix this error, use the Logic ─ Identify DC Nets command and set the voltage value for the VDD net.
After fixing all the DRCs, run the package design integrity checks again to verify that all the issues are resolved. Ensure that the Fix errors automatically option is disabled before running the checks. As you can see in the following figure, all the DRCs are fixed, and no issues are reported in the log file.
Allegro Package Designer Plus has in-built automation capabilities to analyze and quickly resolve wire bonding-specific design issues. Running package integrity checks helps designers fix a lot of manufacturing issues upfront, which can prove to be costly in later stages of the design cycle.
Do SUBSCRIBE to stay updated about upcoming blogs. If there is any topic you want us to cover or any feedback to share, write to us at firstname.lastname@example.org.