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Is it possible to read in a synthesized design in rtlcompiler for
reporting purposes? I know that in synopsys there is a possibility to
read in the .db file and thus not having to re synthesize an old design
for reporting purposes. My synthesis takes several hours and one little
ctrl z by mistake can end the whole session which can be really
you should be able to do the following......after you load your libraries.....read_hdl your_last_verilogread_sdc your_sdc_fileelaboratereport timing li siang
Hi Mike,Li Siang is right, you can easily reload any verilog netlist and write reports. The only one I've seen that doesn't work for this is reporting on power. I've seen that RC doesn't (always) identify the clock-gating correctly, especially if your original setup files set things like the default activity. Timing, Area, Gates and even DFT work fine.Hope this helps,CD
I never managed to read in the .sdc file properly, instead I use my
.tcl constraint files and then It works to some extend. When comparing
my old report files with the new ones most of the paths are the same
but some differ, is this correct or should the report files come out