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reading synthesized design

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Is it possible to read in a synthesized design in rtlcompiler for reporting purposes? I know that in synopsys there is a possibility to read in the .db file and thus not having to re synthesize an old design for reporting purposes. My synthesis takes several hours and one little ctrl z by mistake can end the whole session which can be really frustrating...

/Mike


Originally posted in cdnusers.org by mike.c
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  • I never managed to read in the .sdc file properly, instead I use my .tcl constraint files and then It works to some extend. When comparing my old report files with the new ones most of the paths are the same but some differ, is this correct or should the report files come out identical?

    /Mike


    Originally posted in cdnusers.org by mike.c
Reply

  • I never managed to read in the .sdc file properly, instead I use my .tcl constraint files and then It works to some extend. When comparing my old report files with the new ones most of the paths are the same but some differ, is this correct or should the report files come out identical?

    /Mike


    Originally posted in cdnusers.org by mike.c
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