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reading synthesized design

Is it possible to read in a synthesized design in rtlcompiler for reporting purposes? I know that in synopsys there is a possibility to read in the .db file and thus not having to re synthesize an old design for reporting purposes. My synthesis takes several hours and one little ctrl z by mistake can end the whole session which can be really frustrating...

/Mike

Originally posted in cdnusers.org by mike.c

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archive over 18 years ago

you should be able to do the following

...
...
after you load your libraries
..
...
read_hdl your_last_verilog
read_sdc your_sdc_file
elaborate
report timing

li siang

Originally posted in cdnusers.org by lisiang
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archive over 18 years ago

you should be able to do the following

...
...
after you load your libraries
..
...
read_hdl your_last_verilog
read_sdc your_sdc_file
elaborate
report timing

li siang

Originally posted in cdnusers.org by lisiang
Cancel
Vote Up 0 Vote Down

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