Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Hi everybodyI'm newbie in using Cadence, so pleas forgive me if my question is too banal.I
need to simulate, using Analog Environment, a logic component (so far it's synthetized only in
VHDL) which must control an analog circuit (whose schematic is created by Virtuoso tool). To do this I've imported a
VHDL file into a library of Cadence, and it created the 3 views (entity, structural,
symbol). (CIW -> File -> Import -> VHDL)I put an instance of it in the Virtuoso schematic I want to
simulate by the Analog Environment, but when I start the netlist and simulation, I receive the following error message:Netlister: unable
to descend into any of the views defined in the view list "spectre
cmos_sch cmos.sch schematic veriloga ahdl" for instance ... If
I've uderstood, I must put in the view list in the Environment window
another view, for simulating VHDL imprted, but I have no idea about
which view I have to put in...Thanks in advancePaolo
Paolo,You didn't say which simulator you're trying to use, but from the view list, my guess is that it is spectre.If spectre, you will need a view which is netlistable - for example, a schematic or extracted type view. If it is just VHDL language, you can't simulate that in spectre.When doing File->Import->VHDL, you have the ability to import structural VHDL as "schematic" - did you do that? If you open the structural view that you imported, is it a schematic, or is it textual? If it is a schematic, you should be able to put "structural" in the view list. If it is textual, it's probable that the code is not really structural...If you were using "ams" as the simulator (AMS Designer), then you should be able to simulate it with the language code.Regards,Andrew.
Yes, I'm using Spectre. I've already tried by importing the VHDL as Schematic, but it creates , together with the symbol view, an entity and a behavioral view, and both are textual. And anyway, it continues to show the same error message when I try to simulate.Otherwise, is there an easy way to import a logic circuit, synthetized by vhdl (just an ideal logic, at this stage I don't care about delays and power consumption), into an analog circuit and simulate all by Spectre?Thanks again.Paolo
Paolo,I'm not sure what you mean by synthesizing to "ideal logic", but unless your VHDL instantiates cells which have a transistor level description (e.g. a schematic, or included subckt) or possibly a Verilog-A model, then you cannot simulate in a circuit simulator. You'd need a mixed-signal or logic simulator to do that.From what you say about not caring yet about delays etc, I suspect you have not synthesized to any actual standard cells?Regards,Andrew.
Exactly, I thought it was possible to simulate even without having to create any standard cells (the technology I'm using doesn't give the description of its standard cells). But if this is impossible, I'll look for other solutions.Thanks a lot however, Andrew.Best regardsPaolo