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I've written a nicely scaleable VerilogA module using multi-line busses for the ports and internal 'FOR' loops all parameterized with a pre-processor macro to set the number of ports. The code works nicely, I can set the macro to arbitrary positive values and the module compiles and runs fine.
However, at the moment, I can only set the macro by edding some VerilogA code. Ideally, I would like to define the number of ports as a CDF parameter and pass it down to my module. But as a pre-processor variable is not a standard module parameter, I was not able to find instructions on how to set it from the CDF... Can this be done ?
I have the impression that a good way would be to create a PCell that generates VerilogA views on the fly. Is that possible ? I have already played extensively with PCells generating schematics and symbols -- what about text views or VerilogA ? It seems it is not a support view type in the pcDefinePCell() arguments list...In this fashion each submaster would define a unique module (the nbr of ports would be in the list of formal parameters) which would come in very handy to manage varoius instances of my module with different port numbers...
I did not try this out yet -- would like to understand if that is feasible...
This is really not that straightforward. There are some components in rfLib that do this (e.g. butterworth_lp) - they work by having a custom spectre netlist procedure, which writes out a verilogA model into the netlist directory, using `define to define the parameters, and then includes the common body. They then use a private SKILL function to add this newly generated file to the files which are ahdlInclude'd at the end of the netlist.
Another way is to subclass the formatter, and then define a method for nlPrintFooter to print out the generated verilogA models. But that's not going to be that straightforward either because you need to collect the information in such a way that it works with incremental netlisting.
The best thing is to contact customer support on this one. Then we can give more detailed advice - I'm reluctant to advertise a private SKILL function in a public forum - if you log a service request, we can assess if you need it, and file an enhancement request to ask for that function to be made public in the future.
In reply to Andrew Beckett:
Ok, thanks for the hint. I've already played with custom netlisting to include RLCG files for example. I'll have a look at the filter case. And go to the support line.
OK, I've looked at the filters in the rfLib, and run a testcase. I understand the flow. I have put a support request, describing what I want to do.
In reply to Herge:
Could you provide the Solution ID?
In reply to KoVe:
What solution? There's no solution mentioned as far as I could see...
Herge entered a support request, I (wrongfully) presumed this would results in a solution.
I have a similar problem: I want to make a binary to thermometer decoder and I want the number of outputs ports to be a CDF parameter. This presents two problems.
Indeed, I am not yet aware of a solution allowing to have a PCell that netlists to an underlying scaleable VerilogA module.
What was solved in the above conversation was the question on how to pass a CDF parameter value to a VerilogA pre-processor macro. The method applied in rfLib allows indeed to set pre-processor macro's from CDF parameters, but this is not sufficient to enable a variable number of ports on the VerilogA module during netlisting.
The netlister checks the terminals on the VerilogA view which was set when the view was checked & saved (so using the default number of ports, not the actual one set in CDF). Despite the fact that I have a schematic PCell implementing the correct (dynamic) number of ports, I can not prevent at the moment the netlister to query the (frozen) verilogA view data. I have put a support request (Case# 45438804) on that.