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Using Verilogin

dinac over 16 years ago

hi all,

I am new to cadence, i am trying to simulate the digital-control logic along with the analog in cadence.

I synthesised my vhdl code to verilog netlist using design-compiler, using standard-cell library ".lib"

Now I am trying to import this into the cadence using verilogin. I did not understand the "Reference-Library" in verilogin . Should I create this Reference library from the .lib format standard-cell? Is my flow right? I wanted to do a mix-simulation.

please help

Thanks a lot........

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vjain over 16 years ago

Your standard library should be included in the Library manager before VerilogIn. The name of the "Reference-Library" is the name of the standard cell library as mentioned in Library manager.
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vjain over 16 years ago

Your standard library should be included in the Library manager before VerilogIn. The name of the "Reference-Library" is the name of the standard cell library as mentioned in Library manager.
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