Stats

  • Locked Locked
  • Replies 5
  • Subscribers 126
  • Views 16574
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Using Verilogin

dinac

hi all, 

I am new to cadence, i am trying to simulate the digital-control logic along with the analog in cadence.  

I synthesised my vhdl code to verilog netlist using design-compiler, using standard-cell library ".lib"

Now I am trying to import this into the cadence using verilogin. I did not understand the "Reference-Library" in verilogin . Should I create this Reference library from the .lib format standard-cell?  Is my flow right? I wanted to do a mix-simulation.

please help

Thanks a lot........

  • vjain

    Your standard library should be included in the Library manager before VerilogIn. The name of the "Reference-Library" is the name of the standard cell library as mentioned in Library manager.

  • dinac

    hi vjain,/all

    Thanks for your reply,.

    i did define the library ".lib" location in cds.lib. but when i parse this verilog netlist i get few errors.

    VerilogIn: *W,31 => Module X in FSM_file  not defined.Module FSM_file will be imported as functional.

    VerilogIn: *W,101 => Could not find symbol master for instance XY .Functional view won't have this instance.

    Please help

    thanks

     

  • vjain

    VerilogIn: *W,31 => Module X in FSM_file  not defined.Module FSM_file will be imported as functional.

    This is because there is come submodule of FSM_file which cannot be made with the information you have given. Functional import is done whenever the verilog file has behavioral description.

    Point to remember: Your verilogin file should be gate level netlist only. No behavioral or dataflow models should be there. I hope this should help.

  • dinac

    Thanks for your message....

    The Module X  referes to one my standard cells.

    I still have doubt in the Reference Library part, i do not see any cells in the Library Manager for this Reference Library, is it normal?

     thanks

  • dinac
    Hi

    Thanks for your reply.
    I guess i solved it

    1. Reference Library "CDK"

    2. -V option i provided the link of the standard-cell file in verilog format. ".V"


    I found few errors, mentioning the verilog
    " Verilog definition for module AND2 was not found. Using lib 'techlib' cell 'AND2' view 'symbol' as its symbol.

    But i guess I could discard this.


    Thanks a lot Again

    cheers
    dinac

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.