I am new to cadence, i am trying to simulate the digital-control logic along with the analog in cadence.
I synthesised my vhdl code to verilog netlist using design-compiler, using standard-cell library ".lib"
Now I am trying to import this into the cadence using verilogin. I did not understand the "Reference-Library" in verilogin . Should I create this Reference library from the .lib format standard-cell? Is my flow right? I wanted to do a mix-simulation.
Thanks a lot........
Your standard library should be included in the Library manager before VerilogIn. The name of the "Reference-Library" is the name of the standard cell library as mentioned in Library manager.
Thanks for your reply,.
i did define the library ".lib" location in cds.lib. but when i parse this verilog netlist i get few errors.
VerilogIn: *W,31 => Module X in FSM_file not defined.Module FSM_file will be imported as functional.
VerilogIn: *W,101 => Could not find symbol master for instance XY .Functional view won't have this instance.
This is because there is come submodule of FSM_file which cannot be made with the information you have given. Functional import is done whenever the verilog file has behavioral description.
Point to remember: Your verilogin file should be gate level netlist only. No behavioral or dataflow models should be there. I hope this should help.
Thanks for your message....
The Module X referes to one my standard cells.
I still have doubt in the Reference Library part, i do not see any cells in the Library Manager for this Reference Library, is it normal?