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Using Verilogin

dinac

hi all, 

I am new to cadence, i am trying to simulate the digital-control logic along with the analog in cadence.  

I synthesised my vhdl code to verilog netlist using design-compiler, using standard-cell library ".lib"

Now I am trying to import this into the cadence using verilogin. I did not understand the "Reference-Library" in verilogin . Should I create this Reference library from the .lib format standard-cell?  Is my flow right? I wanted to do a mix-simulation.

please help

Thanks a lot........

Parents

  • VerilogIn: *W,31 => Module X in FSM_file  not defined.Module FSM_file will be imported as functional.

    This is because there is come submodule of FSM_file which cannot be made with the information you have given. Functional import is done whenever the verilog file has behavioral description.

    Point to remember: Your verilogin file should be gate level netlist only. No behavioral or dataflow models should be there. I hope this should help.

Reply

  • VerilogIn: *W,31 => Module X in FSM_file  not defined.Module FSM_file will be imported as functional.

    This is because there is come submodule of FSM_file which cannot be made with the information you have given. Functional import is done whenever the verilog file has behavioral description.

    Point to remember: Your verilogin file should be gate level netlist only. No behavioral or dataflow models should be there. I hope this should help.

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