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Using Verilogin

dinac

hi all, 

I am new to cadence, i am trying to simulate the digital-control logic along with the analog in cadence.  

I synthesised my vhdl code to verilog netlist using design-compiler, using standard-cell library ".lib"

Now I am trying to import this into the cadence using verilogin. I did not understand the "Reference-Library" in verilogin . Should I create this Reference library from the .lib format standard-cell?  Is my flow right? I wanted to do a mix-simulation.

please help

Thanks a lot........

Parents
  • Hi

    Thanks for your reply.
    I guess i solved it

    1. Reference Library "CDK"

    2. -V option i provided the link of the standard-cell file in verilog format. ".V"


    I found few errors, mentioning the verilog
    " Verilog definition for module AND2 was not found. Using lib 'techlib' cell 'AND2' view 'symbol' as its symbol.

    But i guess I could discard this.


    Thanks a lot Again

    cheers
    dinac
Reply
  • Hi

    Thanks for your reply.
    I guess i solved it

    1. Reference Library "CDK"

    2. -V option i provided the link of the standard-cell file in verilog format. ".V"


    I found few errors, mentioning the verilog
    " Verilog definition for module AND2 was not found. Using lib 'techlib' cell 'AND2' view 'symbol' as its symbol.

    But i guess I could discard this.


    Thanks a lot Again

    cheers
    dinac
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