IC6 constraining/placing matched transistors

Hi there,

Is anyone aware if its possible to constrain the placement of transistors for matching such that you can dictate the order of devices and the layer used to space them.

For example i have a schematic with 3 mos device, all of same w/L and 1 finger and 2 multiples.

Schematic:

nm1 m(multiple)=2, nm2 m=2 , dummy1 m=2

I want layout to place/constrain these to align and equally space as:

dummy1.1    nm2.1     nm1.1     nm1.2    nm2.2     dummy1.2

so for example there is polygon in each pcell called OD which i would like NOT to overlap AND be spaced by 1um, so the layout looks like 6 transistors in a line with the OD layers spaced by 1um.

Its basiaclly a simple current mirror with nm1 the bias device in the centre, nm2 split either side & dummy on either end. For matching all 6 units are equally spaced.

Thanks

Stu