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IC6 constraining/placing matched transistors

stuso

Hi there,

Is anyone aware if its possible to constrain the placement of transistors for matching such that you can dictate the order of devices and the layer used to space them.

For example i have a schematic with 3 mos device, all of same w/L and 1 finger and 2 multiples.

Schematic:

nm1 m(multiple)=2, nm2 m=2 , dummy1 m=2

I want layout to place/constrain these to align and equally space as:

dummy1.1    nm2.1     nm1.1     nm1.2    nm2.2     dummy1.2

so for example there is polygon in each pcell called OD which i would like NOT to overlap AND be spaced by 1um, so the layout looks like 6 transistors in a line with the OD layers spaced by 1um.

Its basiaclly a simple current mirror with nm1 the bias device in the centre, nm2 split either side & dummy on either end. For matching all 6 units are equally spaced.

Thanks

Stu

 

  • Hi Stu,

     

    The Modgen functionality in IC 61 is geared precisely to address the requirement you state. It allows users to specify an array of MOS devices or resistors or capacitors, for strucctures such as current miror, differential pair and so on. You can specify rows, columns, interdigitation pattern, dummy devices,body contacts and guard-rings, and specify spacings as necessary. I will be happy to provide more information if you need. 

     

    Thanks, 

    -Sravasti

     

  •  Hi Sarvasti,

    i just happened across the modgen function last night, this is exactly what i need....it sounds like something we would use all the time.

    I only spent half an hour playing around with it but i couldn't quite get it to work yet. I you have time to provide a quick explanation of a simple example (like 3 transistors in a row) i'd really appreciate that. In the meantime i'll keep reading  the manual and messing with the modgen. I'm also interested to know if modgen can handle multiple transistors or does it prefer if you multiply transistors up by doing:

    nm1<0:1> (as opposed to nm1 with m=2)

    Thanks for your reply

    Stu

     

     

     

     

     

  • Hi Stu,

    I will send you a video pointer shortly (I need to upload it to sourcelink design topics), but here is a quick response. 

    To create a Modgen, you simply select the instances in either schematic or layout, and click on the Modgen Editor icon in the toolbar in the Constraint Manager Assistant (it is a cyclic pull-down, the 3rd one in the Schematic Constraint Manager and the 2nd one in the layout Constraint Manager).  This will bring up the Modgen Editor with the instances placed with some default spacing and a single row. You can then specify your own configuration using the various toolbar icons in the Modgen Editor, or the context sensitive menu available through the Right Mouse Button (the icons in the toolbar has tooltips to provide some guidance).  

    You can absolutely use multiplier or m-factor, that is one of the highlights of the Modgen Editor in that it lets you interdigitate them. Or you can also you arrays (e.g. <0:2>) and the Modgen Editor will recognize them as mfactor as long as the devices are connected in parallel as with a multiplier. 

    I will get back to you soon with the video link. Thanks, 

    -Sravasti

  •  Hi Sravasti,

    many thanks for your help, i have it working now. Here are my own notes on how to do for anyone else out there (sorry for the format, its for an internal wiki page):

    MODGEN's Module Generator

    This is a very useful function which allows the designer to dictate the layout of pcells. For example you may have a diff pair(M11&M12) and some dummy's(M19) and you want to space & place them as:

    M19 M11 M12 M12 M11 M19

    M19 M11 M12 M12 M11 M19

    Note each device has a multiple=4

     

    Here is a how to do this

     

    • Open up your schemtic in schematic XL

     

    • From schematic turn on the constraints manager

    Windows -> Assistant -> Constraint manager

     

    • Select the transistors that you wish to place i.e M11,12 & 19

     

    • Within the constraint manager window (lets call that CMW) from the 2nd drop down menu select:

    Placement -> Modgen

    The devices should light up & your new modgen should appear in the CMW.

     

    • Now turn on the module generator

    From the 3rd drop down menu in the CMW select module generator. This should bring up the layout in a new "module generator" window (lets call this MGW).

     

    • Pattern setting

    From within the MGW click the pattern icon at the top, looks like 9 little squares

    1) Click custom

    2) Notice the name mapping

    A : M19 (4)

    B : M11 (4)

    C : M12 (4)

    3) Now set the pattern based on the mapped name:

    A B C C B A

    A B C C B A

    4) Set the orientation of each transistor:

    R0 R0 R0 R0 R0 R0

    R0 R0 R0 R0 R0 R0

    5) Click OK, you should see the devices now placed in the correct order in 2 neat rows.

     

    • Set the transistor spacing

    1) Click the member aligment/spacing (looks like 2 wee transistors)

    2) Click on horizontal & vertical and set both drop-downs to custom

    Now manually enter the spacing required, for example you may wish to space by the minimum OD spacing.

    You CAN use -ve numbers here to overlap devices, infact you will have to.

    4) Your layout should now space neatly as you specified

     

    • Exit the MGW, click the exit icon at the top left

     

    • Click the save botton on the CMW

    This should now be ready for layout. If you want to see it:

     

    • Launch -> Layout XL

     

     

     

  • Hi Stu, 

    Glad to hear that you could get it to work ...  Let me know if you have any follow-up questions (I have a video demo on this which I am trying to promote to Sourcelink Design Topics). Just two quick comments:

    1. Is it your methodology to have actual dummy instances in the schematic?  If so, what you are doing is just fine. But if you think that the circuit designer may not want to have these dummies instantiated in the schematic, then you can use the Modgen's built-in feature to insert dummies automatically (they will not be flagged as mismatches by VLS-XL checks). 

    2. Creating the Modgen constraint from the Constraint Manager pull-down (the 2nd drop-down that lists all the constraint types) is fine, but users could actually directly invoke the Modgen editor (the 3rd drop-down that lists all the special Constraint Editors) after selecting the instances.This would reduce the number of steps for them.

    Good luck! Again, please do not hesitate to ask if you run into any issues. Thanks, 

    -Sravasti

     

  • Thanks for taking the time to reply:

    1) Yes, i'd prefer the dummy's to be in the schematic. Often they will also be used as spares for the next mask respin.  

    2) Sounds good, i'll update my notes

    I'm interested in general idiots guides and videos for IC6, especially as its fairly new for most of us. I stumbled across some IC6 videos that i thought were pretty useful (on source link) & i'd like to see more of this sort of thing. I find the manuals are more useful as a reference for a tool/feature you are already familiar with but not so great for learning from scratch (though that might say more about me!!!)

    Thanks

    Stu 

     

     

     

     

  • Hi Stu, 

    I have been meaning to send you couple of pointers to some video demos posted in Sourcelink, under 'Design Topics' (Custom IC Physical Implementation) but had run into some technicalities. If you are familiar with the Design Topics page, it is probably easy for you to navigate and find these video demos but just in case, here is the link. I don't know if the link will work for sure, if not let me know.

    Specific to Modgens: 

    http://sourcelink.cadence.com/en/search/DisplayHtmlDoc.jhtml;jsessionidsl=K5HAYRALSPQ55LA0BEBCFEQ?param1=http://sourcelink.cadence.com/docs/DTSL/cic_phys_impl/modgenDemo1_index.htm?param2=null?param3=Demos?param4=0?param5=/software/cadence/sldocs/DTSL/cic_phys_impl/modgenDemo1_index.htm@dtsl_en_col?param7=Introduction%20to%20Using%20%3Cb%3EModgens%3C/b%3E%20in%20a%20Front-to-back%20Flow

    The Constraint Driven Flow in general: 

     http://sourcelink.cadence.com/en/search/DisplayHtmlDoc.jhtml;jsessionidsl=K5HAYRALSPQ55LA0BEBCFEQ?param1=http://sourcelink.cadence.com/docs/DTSL/cic_phys_impl/CDNTechDemo_index.htm?param2=null?param3=Demos?param4=0?param5=/software/cadence/sldocs/DTSL/cic_phys_impl/CDNTechDemo_index.htm@dtsl_en_col?param7=Constraint%20Driven%20Physical%20Design:%20A%20Front%20to%20Back%20Flow

    Hope you find this useful ... Thanks, 

    -Sravasti

  •  Very helpful videos, thankyou.

  •  Hi Srivasti,

     I can't see these video links. Can you please post updated links or pointers. Thanks !

    Pranav

     

  • Hi Pranav,

    These links no longer work because the videos were for older releases. I am working with sourcelink to post the updated versions. In the meantime, I will see how I can get them to you more quickly, perhaps through the AE that is working with you.

    Thanks,

    -Sravasti

     

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