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  3. IC6 constraining/placing matched transistors

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IC6 constraining/placing matched transistors

stuso
stuso over 16 years ago

Hi there,

Is anyone aware if its possible to constrain the placement of transistors for matching such that you can dictate the order of devices and the layer used to space them.

For example i have a schematic with 3 mos device, all of same w/L and 1 finger and 2 multiples.

Schematic:

nm1 m(multiple)=2, nm2 m=2 , dummy1 m=2

I want layout to place/constrain these to align and equally space as:

dummy1.1    nm2.1     nm1.1     nm1.2    nm2.2     dummy1.2

so for example there is polygon in each pcell called OD which i would like NOT to overlap AND be spaced by 1um, so the layout looks like 6 transistors in a line with the OD layers spaced by 1um.

Its basiaclly a simple current mirror with nm1 the bias device in the centre, nm2 split either side & dummy on either end. For matching all 6 units are equally spaced.

Thanks

Stu

 

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  • Sravasti
    Sravasti over 16 years ago

    Hi Stu, 

    I have been meaning to send you couple of pointers to some video demos posted in Sourcelink, under 'Design Topics' (Custom IC Physical Implementation) but had run into some technicalities. If you are familiar with the Design Topics page, it is probably easy for you to navigate and find these video demos but just in case, here is the link. I don't know if the link will work for sure, if not let me know.

    Specific to Modgens: 

    http://sourcelink.cadence.com/en/search/DisplayHtmlDoc.jhtml;jsessionidsl=K5HAYRALSPQ55LA0BEBCFEQ?param1=http://sourcelink.cadence.com/docs/DTSL/cic_phys_impl/modgenDemo1_index.htm?param2=null?param3=Demos?param4=0?param5=/software/cadence/sldocs/DTSL/cic_phys_impl/modgenDemo1_index.htm@dtsl_en_col?param7=Introduction%20to%20Using%20%3Cb%3EModgens%3C/b%3E%20in%20a%20Front-to-back%20Flow

    The Constraint Driven Flow in general: 

     http://sourcelink.cadence.com/en/search/DisplayHtmlDoc.jhtml;jsessionidsl=K5HAYRALSPQ55LA0BEBCFEQ?param1=http://sourcelink.cadence.com/docs/DTSL/cic_phys_impl/CDNTechDemo_index.htm?param2=null?param3=Demos?param4=0?param5=/software/cadence/sldocs/DTSL/cic_phys_impl/CDNTechDemo_index.htm@dtsl_en_col?param7=Constraint%20Driven%20Physical%20Design:%20A%20Front%20to%20Back%20Flow

    Hope you find this useful ... Thanks, 

    -Sravasti

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  • Sravasti
    Sravasti over 16 years ago

    Hi Stu, 

    I have been meaning to send you couple of pointers to some video demos posted in Sourcelink, under 'Design Topics' (Custom IC Physical Implementation) but had run into some technicalities. If you are familiar with the Design Topics page, it is probably easy for you to navigate and find these video demos but just in case, here is the link. I don't know if the link will work for sure, if not let me know.

    Specific to Modgens: 

    http://sourcelink.cadence.com/en/search/DisplayHtmlDoc.jhtml;jsessionidsl=K5HAYRALSPQ55LA0BEBCFEQ?param1=http://sourcelink.cadence.com/docs/DTSL/cic_phys_impl/modgenDemo1_index.htm?param2=null?param3=Demos?param4=0?param5=/software/cadence/sldocs/DTSL/cic_phys_impl/modgenDemo1_index.htm@dtsl_en_col?param7=Introduction%20to%20Using%20%3Cb%3EModgens%3C/b%3E%20in%20a%20Front-to-back%20Flow

    The Constraint Driven Flow in general: 

     http://sourcelink.cadence.com/en/search/DisplayHtmlDoc.jhtml;jsessionidsl=K5HAYRALSPQ55LA0BEBCFEQ?param1=http://sourcelink.cadence.com/docs/DTSL/cic_phys_impl/CDNTechDemo_index.htm?param2=null?param3=Demos?param4=0?param5=/software/cadence/sldocs/DTSL/cic_phys_impl/CDNTechDemo_index.htm@dtsl_en_col?param7=Constraint%20Driven%20Physical%20Design:%20A%20Front%20to%20Back%20Flow

    Hope you find this useful ... Thanks, 

    -Sravasti

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