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IC6 constraining/placing matched transistors

stuso

Hi there,

Is anyone aware if its possible to constrain the placement of transistors for matching such that you can dictate the order of devices and the layer used to space them.

For example i have a schematic with 3 mos device, all of same w/L and 1 finger and 2 multiples.

Schematic:

nm1 m(multiple)=2, nm2 m=2 , dummy1 m=2

I want layout to place/constrain these to align and equally space as:

dummy1.1    nm2.1     nm1.1     nm1.2    nm2.2     dummy1.2

so for example there is polygon in each pcell called OD which i would like NOT to overlap AND be spaced by 1um, so the layout looks like 6 transistors in a line with the OD layers spaced by 1um.

Its basiaclly a simple current mirror with nm1 the bias device in the centre, nm2 split either side & dummy on either end. For matching all 6 units are equally spaced.

Thanks

Stu

 

Parents

  • Hi Stu, 

    Glad to hear that you could get it to work ...  Let me know if you have any follow-up questions (I have a video demo on this which I am trying to promote to Sourcelink Design Topics). Just two quick comments:

    1. Is it your methodology to have actual dummy instances in the schematic?  If so, what you are doing is just fine. But if you think that the circuit designer may not want to have these dummies instantiated in the schematic, then you can use the Modgen's built-in feature to insert dummies automatically (they will not be flagged as mismatches by VLS-XL checks). 

    2. Creating the Modgen constraint from the Constraint Manager pull-down (the 2nd drop-down that lists all the constraint types) is fine, but users could actually directly invoke the Modgen editor (the 3rd drop-down that lists all the special Constraint Editors) after selecting the instances.This would reduce the number of steps for them.

    Good luck! Again, please do not hesitate to ask if you run into any issues. Thanks, 

    -Sravasti

     

Reply

  • Hi Stu, 

    Glad to hear that you could get it to work ...  Let me know if you have any follow-up questions (I have a video demo on this which I am trying to promote to Sourcelink Design Topics). Just two quick comments:

    1. Is it your methodology to have actual dummy instances in the schematic?  If so, what you are doing is just fine. But if you think that the circuit designer may not want to have these dummies instantiated in the schematic, then you can use the Modgen's built-in feature to insert dummies automatically (they will not be flagged as mismatches by VLS-XL checks). 

    2. Creating the Modgen constraint from the Constraint Manager pull-down (the 2nd drop-down that lists all the constraint types) is fine, but users could actually directly invoke the Modgen editor (the 3rd drop-down that lists all the special Constraint Editors) after selecting the instances.This would reduce the number of steps for them.

    Good luck! Again, please do not hesitate to ask if you run into any issues. Thanks, 

    -Sravasti

     

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