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Analog Layout: interdigitization

luca magnelli

Hi,

I'm approaching to analog layout with Virtuoso XL. I have to realize the layout of a simple current mirror (2 transistors) and, for matching purposes, I'd like to realize it using an inter-digitized (or common centroid) arrangements.

There is a way, in Virtuoso XL, to merge 2 or more instances in order to form an inter-digitated one? It seems to me that, starting from a schematic entry and generating the layout from this source, Virtuoso XL only gives separate instances and the only thing to do is routing them.

Can anyone show me the procedure for activating transistors inter-digitization in Virtuoso XL?

Thanks,

Luca

Parents
  • Luca, You didn’t state which IC release and database that your using. The solution recommendations will be different between IC 5141 VXL and IC61 VLS XL.   If you are using IC61 VLS XL then there are several ways you can accomplish this task.   First, you can define constraints using either the Circuit Prospector Assistant which will locate occurrences of structures and devices (e.g. current mirror) on the schematic and automatically apply the appropriate constraints. Or you can manually apply the constraints to the structures and devices using the Constraint Manager Assistant. Using the constraints assigned (e.g. Matched Parameters, Symmetry, Module Generator, etc.) You can find both of these documented in the IC613 Virtuoso Unified Custom Constraint User Guide.  There is also a constraint and feature available in VLS GXL called Module Generators or Modgens. Module Generators are designed to provide a way to generate multiple PCell instances into a complex, highly matched and structured array. Modgens are documented in the IC 613 Virtuoso Analog Placement User Guide. 

    If you need assistance I suggest that you contact Cadence Customer Support and/or your local Field Application Engineer.

Reply
  • Luca, You didn’t state which IC release and database that your using. The solution recommendations will be different between IC 5141 VXL and IC61 VLS XL.   If you are using IC61 VLS XL then there are several ways you can accomplish this task.   First, you can define constraints using either the Circuit Prospector Assistant which will locate occurrences of structures and devices (e.g. current mirror) on the schematic and automatically apply the appropriate constraints. Or you can manually apply the constraints to the structures and devices using the Constraint Manager Assistant. Using the constraints assigned (e.g. Matched Parameters, Symmetry, Module Generator, etc.) You can find both of these documented in the IC613 Virtuoso Unified Custom Constraint User Guide.  There is also a constraint and feature available in VLS GXL called Module Generators or Modgens. Module Generators are designed to provide a way to generate multiple PCell instances into a complex, highly matched and structured array. Modgens are documented in the IC 613 Virtuoso Analog Placement User Guide. 

    If you need assistance I suggest that you contact Cadence Customer Support and/or your local Field Application Engineer.

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