Stats

  • Locked Locked
  • Replies 4
  • Subscribers 126
  • Views 17235
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Analog Layout: interdigitization

luca magnelli

Hi,

I'm approaching to analog layout with Virtuoso XL. I have to realize the layout of a simple current mirror (2 transistors) and, for matching purposes, I'd like to realize it using an inter-digitized (or common centroid) arrangements.

There is a way, in Virtuoso XL, to merge 2 or more instances in order to form an inter-digitated one? It seems to me that, starting from a schematic entry and generating the layout from this source, Virtuoso XL only gives separate instances and the only thing to do is routing them.

Can anyone show me the procedure for activating transistors inter-digitization in Virtuoso XL?

Thanks,

Luca

  • Luca, You didn’t state which IC release and database that your using. The solution recommendations will be different between IC 5141 VXL and IC61 VLS XL.   If you are using IC61 VLS XL then there are several ways you can accomplish this task.   First, you can define constraints using either the Circuit Prospector Assistant which will locate occurrences of structures and devices (e.g. current mirror) on the schematic and automatically apply the appropriate constraints. Or you can manually apply the constraints to the structures and devices using the Constraint Manager Assistant. Using the constraints assigned (e.g. Matched Parameters, Symmetry, Module Generator, etc.) You can find both of these documented in the IC613 Virtuoso Unified Custom Constraint User Guide.  There is also a constraint and feature available in VLS GXL called Module Generators or Modgens. Module Generators are designed to provide a way to generate multiple PCell instances into a complex, highly matched and structured array. Modgens are documented in the IC 613 Virtuoso Analog Placement User Guide. 

    If you need assistance I suggest that you contact Cadence Customer Support and/or your local Field Application Engineer.

  •  Unfortunately I'm using IC 5.1.41, can you suggest me a similar procedure for this release?

    Thanks.

    Luca

  • Luca,

    You maybe able to use the constraints in a similar way using the Group and/or Symmetry constraints available in VXL to achieve what you want. Reference the IC 5141 Virtuoso Constraint Manager User Guide.

    Unfortunately Modgens were not implemented in IC5141 VXL. They were found in the NeoCell product.  The majority of the NeoCell 3.4 features including Modgens, Analog Placer, Cell Planner and Constraints/Constraint Manager were integrated into IC61.

  • An automatic interdigitation algorithm is pretty complex unless you use the natural capabilities of abutment in aligningthe cells. Using dbMoveFig or rodAlign on a cell does not trigger abutment during a SKILL program but if you follow the move/align command immediately with hiUpdate(), the abutment/spacing will automatially trigger. Thus, you are spared some of the messy calculations for the pcell parameters as the tool will automatically send the abutment program the correct values. Of course, your abutment program has to be working correctly.

    I do not have the algorithm I used before Cadence bought NeoLinear as it was hard to maintain and NeoCell's capabilities were better (in IC6.1 especially).

     Ted

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.