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Analog Layout: interdigitization

luca magnelli

Hi,

I'm approaching to analog layout with Virtuoso XL. I have to realize the layout of a simple current mirror (2 transistors) and, for matching purposes, I'd like to realize it using an inter-digitized (or common centroid) arrangements.

There is a way, in Virtuoso XL, to merge 2 or more instances in order to form an inter-digitated one? It seems to me that, starting from a schematic entry and generating the layout from this source, Virtuoso XL only gives separate instances and the only thing to do is routing them.

Can anyone show me the procedure for activating transistors inter-digitization in Virtuoso XL?

Thanks,

Luca

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  • Luca,

    You maybe able to use the constraints in a similar way using the Group and/or Symmetry constraints available in VXL to achieve what you want. Reference the IC 5141 Virtuoso Constraint Manager User Guide.

    Unfortunately Modgens were not implemented in IC5141 VXL. They were found in the NeoCell product.  The majority of the NeoCell 3.4 features including Modgens, Analog Placer, Cell Planner and Constraints/Constraint Manager were integrated into IC61.

Reply

  • Luca,

    You maybe able to use the constraints in a similar way using the Group and/or Symmetry constraints available in VXL to achieve what you want. Reference the IC 5141 Virtuoso Constraint Manager User Guide.

    Unfortunately Modgens were not implemented in IC5141 VXL. They were found in the NeoCell product.  The majority of the NeoCell 3.4 features including Modgens, Analog Placer, Cell Planner and Constraints/Constraint Manager were integrated into IC61.

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