VerilogA Problem in MMSIM-7.1

 No, "lib" directory has not been created and I still get the same error from spectre.

 Hi Andrew,

  /tools.lnx86/systemc/gcc/4.1/bin/gcc.t.Z does not exist. I will re-install the package and let you know the results.

 Thanks,

Gokce

 Hi,

 Reinstallation of MMSIM solved these problems. The lib directories are under there now.

 Thanks,

Gokce

Hi !!

I'm having a problem when trying to simulate a verilogA block. Gcc seems to be correctly installed and detected by MMSIM.

We're using MMSIM 7.11 and IC5.1.41 (Cadence 2009-2010 IC package -  icfb 5.1.0 subversion: 5.10.41.500.6.137) within Linux Fedora 11 and with TSMC 0.18um Design Kit loaded.

This error is displayed in Virtuoso Analog Design Env. output log:

Error found by spectre during AHDL read-in.
    ERROR (VACOMP-1008): Cannot compile ahdlcmi module library. Check the log file input.ahdlSimDB/2284_proyecto_TOP_ADCULP_JUNE10_fw1b_veriloga_veriloga.va.fw1b.ahdlcmi/Linux2.6.32.11-99.fc12.x86_64-64+gcc/ for details. If the compiler ran out of memory, use 'setenv CDS_CMI_COMPLEVEL 0', and try again. If the reason for the failure was a syntax error, contact your Cadence Customer Support representative with the netlist, log files, behavioral model files, and any other information that can help identify the problem.

 

... and this is the content of that log file (ahdlcmi.out)

==========================================================================
==========================================================================

ahdlcmicompile: Compiling ahdlcmi in input.ahdlSimDB/2284_proyecto_TOP_ADCULP_JUNE10_fw1b_veriloga_veriloga.va.fw1b.ahdlcmi/Linux2.6.32.11-99.fc12.x86_64-64+gcc/ for Linux2.6.32.11-99.fc12.x86_64-64+gcc with optimize using gcc on Fri May 14 11:29:08 CEST 2010 [5.0]
ahdlcmicompile: Generating makefile

PATH:  /home/cadence/cadence_software/MMSIM/tools.lnx86/systemc/gcc/4.1-x86_64/install/bin:/home/cadence/cadence_software/IC_5.1.41/install/bin.lnx86:/home/cadence/cadence_software/IC_5.1.41/tools/bin:/home/cadence/cadence_software/IC_5.1.41/tools/dfII/bin:/home/cadence/cadence_software/SOC/install/bin.lnx86:/home/cadence/cadence_software/SOC/tools/bin:/home/cadence/cadence_software/SOC/tools/dfII/bin:/home/cadence/cadence_software/MMSIM/install/bin.lnx86:/home/cadence/cadence_software/MMSIM/tools/bin:/home/cadence/cadence_software/MMSIM/tools/dfII/bin:/home/cadence/cadence_software/IUS/install/bin.lnx86:/home/cadence/cadence_software/IUS/tools/bin:/home/cadence/cadence_software/IUS/tools/dfII/bin:/home/cadence/cadence_software/ASSURA_CDB/install/bin.lnx86:/home/cadence/cadence_software/ASSURA_CDB/tools/bin:/home/cadence/cadence_software/ASSURA_CDB/tools/dfII/bin:/usr/lib64/qt-3.3/bin:/usr/kerberos/sbin:/usr/kerberos/bin:/usr/lib64/ccache:/usr/local/bin:/bin:/usr/bin:/usr/local/sbin:/usr/sbin:/sbin:/home/cadence_BIOASICULP/bin

LD_LIBRARY_PATH:  /home/cadence/cadence_software/MMSIM/tools.lnx86/systemc/gcc/4.1-x86_64/install/lib:/home/cadence/cadence_software/MMSIM/tools/lib/64bit:/home/cadence/cadence_software/MMSIM/tools.lnx86/mdl/lib/64bit:/home/cadence/cadence_software/MMSIM/tools.lnx86/mmsim/lib/64bit:/home/cadence/cadence_software/MMSIM/tools.lnx86/inca/lib/64bit:/home/cadence/cadence_software/MMSIM/tools.lnx86/spectre/lib/64bit:/home/cadence/cadence_software/IC_5.1.41/tools/lib/64bit:/home/cadence/cadence_software/MMSIM/tools/lib:/home/cadence/cadence_software/MMSIM/tools.lnx86/mdl/lib:/home/cadence/cadence_software/MMSIM/tools.lnx86/mmsim/lib:/home/cadence/cadence_software/MMSIM/tools.lnx86/inca/lib:/home/cadence/cadence_software/MMSIM/tools.lnx86/spectre/lib:/home/cadence/cadence_software/MMSIM/tools.lnx86/lib/64bit/SuSE:/home/cadence/cadence_software/MMSIM/tools.lnx86/lib/SuSE:/home/cadence/cadence_software/IC_5.1.41/tools/lib:/usr/lib

/home/cadence/cadence_software/MMSIM/tools.lnx86/spectre/ahdlcmi/bin/gnumake -j9 -f GNUmakefile

Compiling C file fw1b_func.c (optimize) with -O0

/home/cadence/cadence_software/MMSIM/tools.lnx86/systemc/gcc/4.1-x86_64/bin/gcc  -march=k8 -ffast-math -O0 -m64 -DSYSV -DSVR4 -D_REENTRANT -fPIC   -DconfigSPECTRE -I. -I/home/cadence/cadence_software/MMSIM/tools.lnx86/spectre/ahdlcmi/include -c fw1b_func.c -o obj/optimize/5.0/fw1b_func.o || rm -f -f obj/optimize/5.0/fw1b_func.o;
Compiling C file fw1b_DcFuncDerLoad.c (optimize)
Compiling C file fw1b_DcFuncLoad.c (optimize)

/home/cadence/cadence_software/MMSIM/tools.lnx86/systemc/gcc/4.1-x86_64/bin/gcc  -march=k8 -ffast-math -O0 -m64 -DSYSV -DSVR4 -
D_REENTRANT -fPIC   -DconfigSPECTRE -I. -I/home/cadence/cadence_software/MMSIM/tools.lnx86/spectre/ahdlcmi/include -c fw1b_DcFuncDerLoad.c -o obj/optimize/5.0/fw1b_DcFuncDerLoad.o || rm -f -f obj/optimize/5.0/fw1b_DcFuncDerLoad.o;

/home/cadence/cadence_software/MMSIM/tools.lnx86/systemc/gcc/4.1-x86_64/bin/gcc  -march=k8 -ffast-math -O0 -m64 -DSYSV -DSVR4 -D_REENTRANT -fPIC   -DconfigSPECTRE -I. -I/home/cadence/cadence_software/MMSIM/tools.lnx86/spectre/ahdlcmi/include -c fw1b_DcFuncLoad.c -o obj/optimize/5.0/fw1b_DcFuncLoad.o || rm -f -f obj/optimize/5.0/fw1b_DcFuncLoad.o;
Compiling C file fw1b_TranFuncDerLoad.c (optimize)

/home/cadence/cadence_software/MMSIM/tools.lnx86/systemc/gcc/4.1-x86_64/bin/gcc  -march=k8 -ffast-math -O0 -m64 -DSYSV -DSVR4 -D_REENTRANT -fPIC   -DconfigSPECTRE -I. -I/home/cadence/cadence_software/MMSIM/tools.lnx86/spectre/ahdlcmi/include -c fw1b_TranFuncDerLoad.c -o obj/optimize/5.0/fw1b_TranFuncDerLoad.o || rm -f -f obj/optimize/5.0/fw1b_TranFuncDerLoad.o;
Compiling C file fw1b_CreateDevice.c (optimize)

/home/cadence/cadence_software/MMSIM/tools.lnx86/systemc/gcc/4.1-x86_64/bin/gcc  -march=k8 -ffast-math -O0 -m64 -DSYSV -DSVR4 -D_REENTRANT -fPIC   -DconfigSPECTRE -I. -I/home/cadence/cadence_software/MMSIM/tools.lnx86/spectre/ahdlcmi/include -c fw1b_CreateDevice.c -o obj/optimize/5.0/fw1b_CreateDevice.o || rm -f -f obj/optimize/5.0/fw1b_CreateDevice.o;
Compiling C file fw1b_TranFuncLoad.c (optimize)

/home/cadence/cadence_software/MMSIM/tools.lnx86/systemc/gcc/4.1-x86_64/bin/gcc  -march=k8 -ffast-math -O0 -m64 -DSYSV -DSVR4 -D_REENTRANT -fPIC   -DconfigSPECTRE -I. -I/home/cadence/cadence_software/MMSIM/tools.lnx86/spectre/ahdlcmi/include -c

fw1b_TranFuncLoad.c -o obj/optimize/5.0/fw1b_TranFuncLoad.o || rm -f -f obj/optimize/5.0/fw1b_TranFuncLoad.o;
fw1b_DcFuncDerLoad.c: In function 'fw1b_DcFuncDerLoad':
fw1b_DcFuncDerLoad.c:38: error: '__tmpStkVar_1' undeclared (first use in this function)
fw1b_DcFuncDerLoad.c:38: error: (Each undeclared identifier is reported only once
fw1b_DcFuncDerLoad.c:38: error: for each function it appears in.)
fw1b_TranFuncDerLoad.c: In function 'fw1b_TranFuncDerLoad':
fw1b_TranFuncDerLoad.c:43: error: '__tmpStkVar_1' undeclared (first use in this function)
fw1b_TranFuncDerLoad.c:43: error: (Each undeclared identifier is reported only once
fw1b_TranFuncDerLoad.c:43: error: for each function it appears in.)
fw1b_func.c: In function 'fw1b_AcLoad':
fw1b_func.c:42: error: '__tmpStkVar_1' undeclared (first use in this function)
fw1b_func.c:42: error: (Each undeclared identifier is reported only once
fw1b_func.c:42: error: for each function it appears in.)

/home/cadence/cadence_software/MMSIM/tools.lnx86/systemc/gcc/4.1-x86_64/bin/gcc -shared -O0 -m64 -fPIC -o obj/optimize/5.0/libahdlcmi.so ./obj/optimize/5.0/fw1b_func.o ./obj/optimize/5.0/fw1b_DcFuncDerLoad.o ./obj/optimize/5.0/fw1b_DcFuncLoad.o ./obj/optimize/5.0/fw1b_TranFuncDerLoad.o ./obj/optimize/5.0/fw1b_TranFuncLoad.o ./obj/optimize/5.0/fw1b_CreateDevice.o  -Wl,-rpath,/usr/lib -Wl,-rpath,/lib -s

gcc: ./obj/optimize/5.0/fw1b_func.o: No such file or directory
gcc: ./obj/optimize/5.0/fw1b_DcFuncDerLoad.o: No such file or directory
gcc: ./obj/optimize/5.0/fw1b_TranFuncDerLoad.o: No such file or directory

gnumake: *** [obj/optimize/5.0/libahdlcmi.so] Error 1

==========================================================================
==========================================================================

As I said, It seems that gcc is working, but it fails when compiling "fw1b_CreateDevice.c". Our code seems to be right, and we could simulate another object from the DK library...

Hope someone can help!! THANKS!!

Regards,
Marcos.

Edited: Information about version added.

Please contact Cadence Customer Support with the data needed to reproduce this, and info on the specific version of MMSIM that you're using (you didn't say).

I've not found any similar reports - it's different from the previous problems in this thread (so it probably would have made more sense for this to be a new thread). It's quite likely a bug (may have been fixed - can't tell without the data or knowing which version you're using).

Regards,

Andrew.

Hello Andrew,

Thanks for your fast response. Sorry, I forgot to add that info. We're using MMSIM 7.11 and IC5.1.41 (Cadence 2009-2010 IC package -  icfb 5.1.0 subversion: 5.10.41.500.6.137) within Linux Fedora 11 and with TSMC 0.18um Design Kit loaded.

Anyway, I'll contact with Cadence Customer Support with the steps to reproduce as you said.

Thanks Again.

Regards,
Marcos. 

PS: You're right so... maybe an admin could move this three messages to a new topic...  

Marcos,

I tried splitting this off, but something went wrong and it got rather confused - so I re-merged it again. I'll leave it alone for now...

Bear in mind that Fedora 11 is not a supported OS, but I think this issue is likely to occur on any platform with the specific VerilogA you're using  (that's my guess anyway).

Regards,

Hello Andrew!

I have some good news regarding this topic.

The problem was that we could simulate some verilog blocks but it fails with 3 specific ones. Then, we tried to simulate those ones in another computer where we have Cadence installed, and it worked. The diference between those machines is that we have an older version of MMSIM (7.01) where it worked, and a latter version (7.11) where it wasn't.

I checked it by installing the older version of MMSIM in the first machine and then I switched the "environment PATH" between older and newer version of MMSIM. Then I confirmed that:

MMSIM 7.11HF188 - Not working for us. We have the described problem.

MMSIM 7.01HF076 - Working correctly.

Anyway, I don't know nothing about verilog because I work with schematics and layouts, so I still have to talk with my mate and confirm all of this. After that, I will post any news.

Regards,
Marcos.

Hi Marcos,

If something is broken in the newer version, then first I'd try the latest hotfix (to see if it has been fixed) and then you should contact Customer Support as I advised earlier.

Regards,

Andrew.