• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. problems with display settings

Stats

  • Locked Locked
  • Replies 4
  • Subscribers 125
  • Views 13578
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

problems with display settings

Peach99
Peach99 over 16 years ago

Hi, I have a very important question about  the display setting of waveform (ADE). I know that I can change the colors in the display.drf - file, but my question is how I can set more different colors? I already know when I have more graphs as colors the line style changes automatically, but i want more then ten colors. And one another question is, how I can stop a simulation with a conditionally break. What I mean is, where I can enter a function or the like in the simulation settings, where I can define a break condition and how I can do this. For example I want to break a simulation if the graph reach a certain voltage value . Please help me! I don't know, how I can do this!

Regards

Daniel Pietsch 

  • Cancel
Parents
  • Andrew Beckett
    Andrew Beckett over 16 years ago

    I'd be wary of depending on the VerilogA debugger, because it's been end-of-lifed.

    For VerilogA, you could write a model which monitored the node, and then invoked $stop or $finish to tell the simulator to end when that condition was reached.

    This is also something that is doable with SpectreMDL - but if you're an ADE user, that's probably not a good solution for you.

    For more information on VerilogA, look in the documentation, but also you may find A Designer's Guide to VerilogAMS useful as a place to learn more about the language.

    Regards,

    Andrew.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • Andrew Beckett
    Andrew Beckett over 16 years ago

    I'd be wary of depending on the VerilogA debugger, because it's been end-of-lifed.

    For VerilogA, you could write a model which monitored the node, and then invoked $stop or $finish to tell the simulator to end when that condition was reached.

    This is also something that is doable with SpectreMDL - but if you're an ADE user, that's probably not a good solution for you.

    For more information on VerilogA, look in the documentation, but also you may find A Designer's Guide to VerilogAMS useful as a place to learn more about the language.

    Regards,

    Andrew.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information