Stats

  • Locked Locked
  • Replies 7
  • Subscribers 126
  • Views 16361
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

A quetion of post layout simulation

Tinaliao

After schematic simulation and layout extraction, I got an extracted layout, and then I did the LVS. Finally I want to do the post layout simulation using my extracted layout. 

 However, I have two problems.

 1. I found that if I don't add the model library, e.g., the ami06P and ami06N, the simulation can't succeed. But  I think using ami06P and ami06N, it is using the existing models rather than the layout I draw. (I already changed the environment to be "spectre comos_sch cmos.sch extracted schematic veriloga ahdl").

2.  In addition, the simulation using the extracted layout just outputs a voltage of 0 V and the input and output current of the layout are both 0 A. I don't know the reason.

 Thank you very much.

Parents
  • Hi Quek,

    Thank you very much for you answer. For the setup->environment, the information in "switch view list" is: spectre cmos_sch cmos. sch extracted schematic veriloga, and the information in "stop view list" is spectre.

    What is the view name? I named my circuit as extracted1.

    After "simulation->netlist->create raw",  I can see like "(vin vout) capacitor c=2.34363-16 m=1
    (vin gnd) capacitor c=2.3436 m=1" etc.  Is this right?

    And what's next I can check? The current into and out of my extracted circuit are all flow, and I think it may be because the contact or via connecting different layer has some problem.

    Thanks again,
    Chen
Reply
  • Hi Quek,

    Thank you very much for you answer. For the setup->environment, the information in "switch view list" is: spectre cmos_sch cmos. sch extracted schematic veriloga, and the information in "stop view list" is spectre.

    What is the view name? I named my circuit as extracted1.

    After "simulation->netlist->create raw",  I can see like "(vin vout) capacitor c=2.34363-16 m=1
    (vin gnd) capacitor c=2.3436 m=1" etc.  Is this right?

    And what's next I can check? The current into and out of my extracted circuit are all flow, and I think it may be because the contact or via connecting different layer has some problem.

    Thanks again,
    Chen
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.