Stats

  • Locked Locked
  • Replies 7
  • Subscribers 126
  • Views 16326
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

A quetion of post layout simulation

Tinaliao

After schematic simulation and layout extraction, I got an extracted layout, and then I did the LVS. Finally I want to do the post layout simulation using my extracted layout. 

 However, I have two problems.

 1. I found that if I don't add the model library, e.g., the ami06P and ami06N, the simulation can't succeed. But  I think using ami06P and ami06N, it is using the existing models rather than the layout I draw. (I already changed the environment to be "spectre comos_sch cmos.sch extracted schematic veriloga ahdl").

2.  In addition, the simulation using the extracted layout just outputs a voltage of 0 V and the input and output current of the layout are both 0 A. I don't know the reason.

 Thank you very much.

  •  1. use hierarchy editor to configure your PLS testbench

    2. do you have the pins on the correct layers?

  • Thank you very much for your answer.

    1. Where is the hierarchy editor? and how to configure it?

    2. For the vdd and gnd, I use "metal1" to add pin.
    For the Vin and Vout, I use "metal2" to add pin, and use "via" to connect them with some "metal1" layer.
    For the connection place of poly and metal1, I use "cc" to connect them. I am not sure whether this is right or not?

  •  Hi Tina

    The hierarchy editor (HE) will be launched when you create a "config" view. In the library manager, go to "File->Create->New cellview" and set the tool as "Hierarchy-Editor". But I think perhaps the HE might not be needed for your case.

    Regardless of whether you use the schematic or extracted view for simulation, you will always need to include the model files. You wrote that you have already included "extracted" view in the environment. This should normally suffice as a simple way of simulating an extracted view without going through the HE.

    Just to be sure that your settings are correct, would you please go to "Setup->Environment" and provide the info in the "Switch View List" and "Stop View List" fields? Thanks.

    Is the view named as "extracted" or "av_extracted" or is it some other name?

    If you display the netlist using "Simulation->Netlist->Create", do you see many parasitic R and C in it?

    Let's first confirm if you can netlist the extracted view correctly. : )

    Best regards
    Quek

  • Hi Quek,

    Thank you very much for you answer. For the setup->environment, the information in "switch view list" is: spectre cmos_sch cmos. sch extracted schematic veriloga, and the information in "stop view list" is spectre.

    What is the view name? I named my circuit as extracted1.

    After "simulation->netlist->create raw",  I can see like "(vin vout) capacitor c=2.34363-16 m=1
    (vin gnd) capacitor c=2.3436 m=1" etc.  Is this right?

    And what's next I can check? The current into and out of my extracted circuit are all flow, and I think it may be because the contact or via connecting different layer has some problem.

    Thanks again,
    Chen

  • Tinaliao said:
    What is the view name? I named my circuit as extracted1.

     

    If it is the cellview name, then you should be putting extracted1 into the switch view list. If it is the cell name, you need to find out what cellview is created by your extraction tool and add that to switch view list.

    What tool are you using to extract? Diva? RCX? QRC? Diva will call the extracted cellview "extracted", QRC (and I believe RCX) will call it "av_extracted". I know that If you used QRC and told it to extract parasitics, they should appear in the netlist as pcapacitor, presistor, pinductor, pmind. 

  • Note that both Diva and QRC allow you to call the view whatever you want - the default is just "extracted" or "av_extracted".

    Just a minor point; still needs the view name in the switch list (or hierarchy editor) to be correct.

    Regards,

    Andrew
  • Hi tkan,

    Thank you very much. Previously I did not know I should add the name of the extracted circuit in the switch view list. I thought "extracted" just means that it simulates the extracted circuit.

    Now the problem is solved. :-)  Your answer is very helpful, thanks a again.

    Best,
    Tina

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.