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Mixed simulations + vhdl

Hi all,

I'm starting mixed simulations and I don't manage to get them working if the source code is in vhdl. I use spectreVerilog for everything and I manage to get it working fine with a verilog source, but not in vhdl.

Is there something different needed for a vhdl source??

Andrew Beckett over 15 years ago

Yes, AMS Designer (simulator "ams" in ADE). Look in the documentation for more details.
spectreVerilog is a very old interface, and only supports Verilog (years and years ago it used to (sort of) support VHDL via a VHDL Import capability in Verilog, but it was very problematic and no longer is supported (and hasn't been for many years).
Regards,
Andrew.
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acomerma over 15 years ago

Thanks!! it seems to work perfectly!

Albert
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