• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. Manual editing of a p2lvsfile

Stats

  • Locked Locked
  • Replies 6
  • Subscribers 125
  • Views 7411
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Manual editing of a p2lvsfile

Slawa
Slawa over 15 years ago

 Hello

 After I have faced the following error: ERROR (LBMISC-215480): at "RCXdspf": LVS connectivity file /.../  is missing .2. in the course of start qrc at me there was a necessity of editing p2lvsfile.

In a "ICT.file" is
  # Diffusion Layers
diffusion NP {thickness, resistivity} and

 # dielectric Layers
dielectric   STI {conformal FALSE, height, thickness, dielectric_constant}.

How they are necessary for setting in p2lvsfile if to them as a matter of fact corresponds nothing in a RULEfile? 

 How to be with layers which are created directly in RULEfile but are used in LVSFILE? For example there is layer PACTIVE=Layer1 and (Layer2 or Layer3) which is set in RULEfile and in LVSFILE it is used only as:

 model = diode[DP],DP
element diode[DP] DPPLUS PACTIVE NWELL

 It turns out that in LVSFILE there is no information on the given layer as well as there is no information on it in ICT.

 

Best regards

Beginner engineer from Russia 

  • Cancel
  • Quek
    Quek over 15 years ago

    Hi Slawa

    I don't quite understand the question so I am going to make a guess:

    You are wondering how the layers in the ictfile relates to the layers used in the rules file. The layers in the ictfile are termed as "process layers". The layers in the rules file are termed as "lvs layers" and are created for the purpose of lvs verification. These layers must be mapped to the actual process layer using the p2lvsfile or layer_setup file so that parasitic R and C can be calculated. E.g. by mapping lvs layers "m1" and "m2" to process layers "Metal1" and "Metal2" in the layer_setup file, qrc will know the distance between m1 and m2 through the thickness values in the ictfile and hence parasitic caps can be calculated.

    lvs layers that are used in the mapping file should also be found in the lvsfile. Otherwise there will be compilation errors. Hope that this answers your questions.

    Best regards
    Quek

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Slawa
    Slawa over 15 years ago

    Hello Quek

    In the question I spoke about those layers which is in ICTfile but are not present in LVSfile and also about layers "intermediate" which are created in LVSrule. That is, there are base layers of process: M1 M2 V1 V2 Poly DIFF diffRES NP etc, and there are layers which in LVSrule are created on their basis by certain rules (or, and, not). Here for example:

    //////////////RULE_file//////////////////
    NDIFF = DIFF AND NP
    NACTIVE = NDIFF NOT diffRes


    Where DIFF, NP and diffRES - base layers of the given technology and layer NACTIVE it is created  on their basis directly for verification.
    In LVSfile about layer NACTIVE it it is not known, It is present but about its structure there is no information. 

    ///////////LVS_file///////////
    connect M1 NACTIVE by CON

    model = mos [NH], NH
    element mos [NH] NGATEGX3 GP NACTIVE PSUB
    Therefore my question also is devoted that how to declare the given layer in p2lvsfile

     

     On the first question:
    In ICTfile there are layers which corresponds nothing in LVSfile. For example:

    /////////////////ICTfile///////////////////////
    # Diffusion Layers
    diffusion NPJunc {
       thickness         ///
       resistivity       ////
    }
    # dielectric Layers
    dielectric   STI {
       conformal            FALSE
       height               ////
       thickness            ////
       dielectric_constant        ////
    } 

     How to designate the given layers in p2lvsfile and whether it is necessary to designate them in general.

     If them to ignore in p2lvsfile that Techgen writes:

     WARNING (CAPGEN-41446): Substrate layer 'STI' will be automatically generated
     during extraction due to incomplete p2lvs mapping. This may lead to unintended results.

     

    Best regards

    Beginner engineer from Russia 

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Quek
    Quek over 15 years ago

    Hi Slawa

    You will only need the layers that are listed in the lvsfile. There are many layers in the rules file and as you have noted, most are just intermediate layers that need not be mapped. The lvsfile rules file contains the important lvs layers that directly contribute to connectivity and device formation. Some level of knowlege regarding the rule deck layers is needed in order to do the mapping in the layer_setup file.

    The interconnect lvs layers are easy because they usually have names such as "m1_conn" or "m1" or "metal1", etc. For the other process layers such as such as STI and NPJunc, we have to figure out the corresponding lvs layers. Look for names such as source_drain, sd, psub, substrate, etc. In the lvsfile, take note of the layers that are connected through "contact" layer. Usually you would want to map such layers (e.g. psub, nimp, pimp, etc) to the process layers that represent substrate and diffusion.

    By the way, please do not use p2lvsfile format as it has already been replaced by layer_setup file. You must provde some mapping to all process layers so that the extraction results can be accurate.

    Best regards
    Quek

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Slawa
    Slawa over 15 years ago

    Many thanks for the help. QRC successfully started. And concerning replacement p2lvsfile on layer_setup_file... unfortunately compilation in such mode (are not created RCXpsiceINIT, RCXdspfINIT). About the given problem I wrote in theme Techgen + RCXdspfINIT.

     How to be if a layer in ICT corresponds at once to two layers in LVSFILE? How it to define in p2lvsfile?

    As has been mentioned layer_setup_file I will dare to ask at once a question not to create a separate theme. Whether identical structure at it in comparison with p2lvsfile? A method of experiment I have revealed only one difference... This requirement at one of them to " ; "at the end of line

     

    Best regards

    Beginner engineer from Russia 

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Quek
    Quek over 15 years ago

    Hi Slawa

    I am also not sure about the cause of your compilation problem. Perhaps it would be good to get some help from Cadence support.

    You can map multiple lvs layers to a single process layer as follows:
    pro_layer=STI   ext_layer=nwell_conn,Nburied,psubstrate

    Some p2lvsfile features such as specification of rho, temperature coefficient, etc have been shifted to the ictfile because we now use ictfile for both cell and transistor level simulation. Since you are learning about Techgen and QRC, it would really be better if you can start with layer_setup file and not p2lvsfile. The lack of a semi-colon at the end of the line in layer_setup file is just one of the differences that it has with p2lvsfile.

    Best regards
    Quek

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Slawa
    Slawa over 15 years ago

     Many thanks for the help

     

    Best regards

    Beginner engineer from Russia 

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information